R-Car Gen3 and Gen4 have some differences in the mask bits. Add a
mask table to handle these differences.
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
v4->v5:
* Improved commit description by replacing has->have.
* Collected tag.
* Dropped RCANFD_EEF_MASK and RCANFD_RNC_MASK as it is taken
care by gpriv->channels_mask and info->num_supported_rules.
v3->v4:
* Added prefix RCANFD_* to enum rcar_canfd_mask_id.
v3:
* New patch.
---
drivers/net/can/rcar/rcar_canfd.c | 53 ++++++++++++++++++++++++++-----
1 file changed, 45 insertions(+), 8 deletions(-)
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index 1ba79f424fb3..e019e941122f 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -94,7 +94,7 @@
/* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
#define RCANFD_GAFLECTR_AFLDAE BIT(8)
-#define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & reg_gen4(gpriv, 0x7f, 0x1f))
+#define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & (gpriv)->info->mask_table[RCANFD_AFLPN_MASK])
/* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
#define RCANFD_GAFLID_GAFLLB BIT(29)
@@ -112,13 +112,13 @@
/* RSCFDnCFDCmNCFG - CAN FD only */
#define RCANFD_NCFG_NTSEG2(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
+ (((x) & (gpriv)->info->mask_table[RCANFD_NTSEG2_MASK]) << reg_gen4(gpriv, 25, 24))
#define RCANFD_NCFG_NTSEG1(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
+ (((x) & (gpriv)->info->mask_table[RCANFD_NTSEG1_MASK]) << reg_gen4(gpriv, 17, 16))
#define RCANFD_NCFG_NSJW(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
+ (((x) & (gpriv)->info->mask_table[RCANFD_NSJW_MASK]) << reg_gen4(gpriv, 10, 11))
#define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
@@ -180,13 +180,13 @@
#define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
/* RSCFDnCFDCmDCFG */
-#define RCANFD_DCFG_DSJW(gpriv, x) (((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
+#define RCANFD_DCFG_DSJW(gpriv, x) (((x) & (gpriv)->info->mask_table[RCANFD_DSJW_MASK]) << 24)
#define RCANFD_DCFG_DTSEG2(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
+ (((x) & (gpriv)->info->mask_table[RCANFD_DTSEG2_MASK]) << reg_gen4(gpriv, 16, 20))
#define RCANFD_DCFG_DTSEG1(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
+ (((x) & (gpriv)->info->mask_table[RCANFD_DTSEG1_MASK]) << reg_gen4(gpriv, 8, 16))
#define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
@@ -228,7 +228,7 @@
/* RSCFDnCFDCFCCk */
#define RCANFD_CFCC_CFTML(gpriv, x) \
- (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
+ (((x) & (gpriv)->info->mask_table[RCANFD_CFTML_MASK]) << reg_gen4(gpriv, 16, 20))
#define RCANFD_CFCC_CFM(gpriv, x) (((x) & 0x3) << reg_gen4(gpriv, 8, 16))
#define RCANFD_CFCC_CFIM BIT(12)
#define RCANFD_CFCC_CFDC(gpriv, x) (((x) & 0x7) << reg_gen4(gpriv, 21, 8))
@@ -512,9 +512,21 @@ enum rcar_canfd_reg_offset_id {
RCANFD_CFOFFSET, /* Transmit/receive FIFO buffer access ID register */
};
+enum rcar_canfd_mask_id {
+ RCANFD_AFLPN_MASK, /* Acceptance Filter List Page Number */
+ RCANFD_NTSEG2_MASK, /* Nominal Bit Rate Time Segment 2 Control */
+ RCANFD_NTSEG1_MASK, /* Nominal Bit Rate Time Segment 1 Control */
+ RCANFD_NSJW_MASK, /* Nominal Bit Rate Resynchronization Jump Width Control */
+ RCANFD_DSJW_MASK, /* Data Bit Rate Resynchronization Jump Width Control */
+ RCANFD_DTSEG2_MASK, /* Data Bit Rate Time Segment 2 Control */
+ RCANFD_DTSEG1_MASK, /* Data Bit Rate Time Segment 1 Control */
+ RCANFD_CFTML_MASK, /* Common FIFO TX Message Buffer Link */
+};
+
struct rcar_canfd_global;
struct rcar_canfd_hw_info {
+ const u32 *mask_table;
const u16 *regs;
u16 num_supported_rules;
u8 rnc_field_width;
@@ -615,7 +627,30 @@ static const u16 rcar_gen4_regs[] = {
[RCANFD_CFOFFSET] = 0x6400,
};
+static const u32 rcar_gen3_mask_table[] = {
+ [RCANFD_AFLPN_MASK] = 0x1f,
+ [RCANFD_NTSEG2_MASK] = 0x1f,
+ [RCANFD_NTSEG1_MASK] = 0x7f,
+ [RCANFD_NSJW_MASK] = 0x1f,
+ [RCANFD_DSJW_MASK] = 0x7,
+ [RCANFD_DTSEG2_MASK] = 0x7,
+ [RCANFD_DTSEG1_MASK] = 0xf,
+ [RCANFD_CFTML_MASK] = 0xf,
+};
+
+static const u32 rcar_gen4_mask_table[] = {
+ [RCANFD_AFLPN_MASK] = 0x7f,
+ [RCANFD_NTSEG2_MASK] = 0x7f,
+ [RCANFD_NTSEG1_MASK] = 0xff,
+ [RCANFD_NSJW_MASK] = 0x7f,
+ [RCANFD_DSJW_MASK] = 0xf,
+ [RCANFD_DTSEG2_MASK] = 0xf,
+ [RCANFD_DTSEG1_MASK] = 0x1f,
+ [RCANFD_CFTML_MASK] = 0x1f,
+};
+
static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
+ .mask_table = rcar_gen3_mask_table,
.regs = rcar_gen3_regs,
.num_supported_rules = 256,
.rnc_field_width = 8,
@@ -625,6 +660,7 @@ static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
};
static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
+ .mask_table = rcar_gen4_mask_table,
.regs = rcar_gen4_regs,
.num_supported_rules = 512,
.rnc_field_width = 16,
@@ -636,6 +672,7 @@ static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
};
static const struct rcar_canfd_hw_info rzg2l_hw_info = {
+ .mask_table = rcar_gen3_mask_table,
.regs = rcar_gen3_regs,
.num_supported_rules = 256,
.rnc_field_width = 8,
--
2.43.0
