The esdACC CAN-FD FPGA versions below revision 0.72 (0x0048) have some
features missing:
- Older versions have only a 8-bit wide BRP. Therefore its maximum value
is 256 instead of 512.
- Older versions don't implement the TDC filter logic.
Also the DAR feature (single shot) is implemented only for esdACC
versions 0.72 and later for the Classic CAN and CAN FD variants.
Signed-off-by: Stefan Mätje <stefan.maetje@xxxxxx>
---
drivers/net/can/esd/esd_402_pci-core.c | 65 ++++++++++++++++++++++----
1 file changed, 55 insertions(+), 10 deletions(-)
diff --git a/drivers/net/can/esd/esd_402_pci-core.c b/drivers/net/can/esd/esd_402_pci-core.c
index 03df04251c03..1152182aa64a 100644
--- a/drivers/net/can/esd/esd_402_pci-core.c
+++ b/drivers/net/can/esd/esd_402_pci-core.c
@@ -95,6 +95,32 @@ static const struct can_bittiming_const pci402fd_data_bittiming_const = {
.brp_inc = 1,
};
+/* Used if the esdACC FPGA is built as CAN-FD version, for versions pre 0.72. */
+/* These older versions have a maximum BRP of 256. */
+static const struct can_bittiming_const pci402fd_pre72_nom_bittiming_const = {
+ .name = "esd_402fd",
+ .tseg1_min = 1,
+ .tseg1_max = 256,
+ .tseg2_min = 1,
+ .tseg2_max = 128,
+ .sjw_max = 128,
+ .brp_min = 1,
+ .brp_max = 256,
+ .brp_inc = 1,
+};
+
+static const struct can_bittiming_const pci402fd_pre72_data_bittiming_const = {
+ .name = "esd_402fd",
+ .tseg1_min = 1,
+ .tseg1_max = 32,
+ .tseg2_min = 1,
+ .tseg2_max = 16,
+ .sjw_max = 16,
+ .brp_min = 1,
+ .brp_max = 256,
+ .brp_inc = 1,
+};
+
/* Transmitter Delay Compensation constants for esdACC controller
*/
static const struct can_tdc_const pci402fd_tdc_const = {
@@ -106,6 +132,18 @@ static const struct can_tdc_const pci402fd_tdc_const = {
.tdcf_max = 63,
};
+/* Transmitter Delay Compensation constants for esdACC controller
+ * for versions pre 0.72. No TDC Filter register present.
+ */
+static const struct can_tdc_const pci402fd_pre72_tdc_const = {
+ .tdcv_min = 0,
+ .tdcv_max = 0,
+ .tdco_min = 0,
+ .tdco_max = 63,
+ .tdcf_min = 0,
+ .tdcf_max = 0,
+};
+
static const struct net_device_ops pci402_acc_netdev_ops = {
.ndo_open = acc_open,
.ndo_stop = acc_close,
@@ -202,6 +240,11 @@ static int pci402_init_card(struct pci_dev *pdev)
card->ov.version);
return -EINVAL;
}
+ if (card->ov.version < PCI402_FPGA_VER_0_72) {
+ pci_warn(pdev,
+ "esdACC below version 0x%.4x misses some features, please update from 0x%.4x\n",
+ PCI402_FPGA_VER_0_72, card->ov.version);
+ }
if (card->ov.timestamp_frequency != ACC_TS_FREQ_80MHZ) {
pci_err(pdev,
@@ -223,13 +266,7 @@ static int pci402_init_card(struct pci_dev *pdev)
if (card->ov.features & ACC_OV_REG_FEAT_MASK_CANFD) {
pci_warn(pdev,
- "esdACC with CAN-FD feature detected. This driver partly implements CAN-FD.\n");
- if (card->ov.version < PCI402_FPGA_VER_0_72) {
- pci_err(pdev,
- "esdACC CAN-FD below version 0x%.4x not supported, please update from 0x%.4x\n",
- PCI402_FPGA_VER_0_72, card->ov.version);
- return -EINVAL;
- }
+ "esdACC with CAN-FD feature detected. This driver is not feature complete, yet.\n");
}
#ifdef __LITTLE_ENDIAN
@@ -410,9 +447,17 @@ static int pci402_init_cores(struct pci_dev *pdev)
priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD |
CAN_CTRLMODE_TDC_AUTO |
CAN_CTRLMODE_TDC_MANUAL;
- priv->can.bittiming_const = &pci402fd_nom_bittiming_const;
- priv->can.data_bittiming_const = &pci402fd_data_bittiming_const;
- priv->can.tdc_const = &pci402fd_tdc_const;
+
+ if (card->ov.version >= PCI402_FPGA_VER_0_72) {
+ priv->can.bittiming_const = &pci402fd_nom_bittiming_const;
+ priv->can.data_bittiming_const = &pci402fd_data_bittiming_const;
+ priv->can.tdc_const = &pci402fd_tdc_const;
+ } else {
+ priv->can.bittiming_const = &pci402fd_pre72_nom_bittiming_const;
+ priv->can.data_bittiming_const =
+ &pci402fd_pre72_data_bittiming_const;
+ priv->can.tdc_const = &pci402fd_pre72_tdc_const;
+ }
priv->can.do_get_auto_tdcv = acc_get_auto_tdcv;
} else {
priv->can.bittiming_const = &pci402_bittiming_const;
--
2.34.1
