On 18.09.2024 16:21:54, Matthias Schiffer wrote:
> The interrupt line of PCI devices is interpreted as edge-triggered,
> however the interrupt signal of the m_can controller integrated in Intel
> Elkhart Lake CPUs appears to be generated level-triggered.
>
> Consider the following sequence of events:
>
> - IR register is read, interrupt X is set
> - A new interrupt Y is triggered in the m_can controller
> - IR register is written to acknowledge interrupt X. Y remains set in IR
>
> As at no point in this sequence no interrupt flag is set in IR, the
> m_can interrupt line will never become deasserted, and no edge will ever
> be observed to trigger another run of the ISR. This was observed to
> result in the TX queue of the EHL m_can to get stuck under high load,
> because frames were queued to the hardware in m_can_start_xmit(), but
> m_can_finish_tx() was never run to account for their successful
> transmission.
>
> To fix the issue, repeatedly read and acknowledge interrupts at the
> start of the ISR until no interrupt flags are set, so the next incoming
> interrupt will also result in an edge on the interrupt line.
>
> Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake")
> Signed-off-by: Matthias Schiffer <matthias.schiffer@xxxxxxxxxxxxxxx>
> ---
> drivers/net/can/m_can/m_can.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
> index 47481afb9add3..363732517c3c5 100644
> --- a/drivers/net/can/m_can/m_can.c
> +++ b/drivers/net/can/m_can/m_can.c
> @@ -1207,20 +1207,28 @@ static void m_can_coalescing_update(struct m_can_classdev *cdev, u32 ir)
> static int m_can_interrupt_handler(struct m_can_classdev *cdev)
> {
> struct net_device *dev = cdev->net;
> - u32 ir;
> + u32 ir = 0, ir_read;
> int ret;
>
> if (pm_runtime_suspended(cdev->dev))
> return IRQ_NONE;
>
> - ir = m_can_read(cdev, M_CAN_IR);
> + /* For m_can_pci, the interrupt line is interpreted as edge-triggered,
> + * but the m_can controller generates them as level-triggered. We must
> + * observe that IR is 0 at least once to be sure that the next
> + * interrupt will generate an edge.
> + */
> + while ((ir_read = m_can_read(cdev, M_CAN_IR)) != 0) {
> + ir |= ir_read;
> +
> + /* ACK all irqs */
> + m_can_write(cdev, M_CAN_IR, ir);
> + }
This probably causes a measurable overhead on peripheral devices, think
about limiting this to !peripheral devices or introduce a new quirk that
is only set for the PCI devices.
Marc
> +
> m_can_coalescing_update(cdev, ir);
> if (!ir)
> return IRQ_NONE;
>
> - /* ACK all irqs */
> - m_can_write(cdev, M_CAN_IR, ir);
> -
> if (cdev->ops->clear_interrupts)
> cdev->ops->clear_interrupts(cdev);
>
> --
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