Kvaser's PCIe cards uses the KCAN FPGA IP block which has dual 4K buffers for
incoming messages shared by all (currently up to eight) channels. While the
driver processes messages in one buffer, new incoming messages are stored in
the other and so on.
The design of KCAN is such that a buffer must be fully read and then released.
Releasing a buffer will make the FPGA switch buffers. If the other buffer
contains at least one incoming message the FPGA will also instantly issue a
new interrupt, if not the interrupt will be issued after receiving the first
new message.
With IRQx interrupts, it takes a little time for the interrupt to happen,
enough for any previous ISR call to do it's business and return, but MSI
interrupts are way faster so this time is reduced to almost nothing.
So with MSI, releasing the buffer HAS to be the very last action of the ISR
before returning, otherwise the new interrupt might be "masked" by the kernel
because the previous ISR call hasn't returned. And the interrupts are edge-
triggered so we cannot loose one, or the ping-pong reading process will stop.
This is why this patch modifies the driver to use a single write to the SRB_CMD
register before returning.
Signed-off-by: Martin Jocic <martin.jocic@xxxxxxxxxx>
---
Changes in v2:
* Added explanation to commit message text as requested, no code change!
drivers/net/can/kvaser_pciefd.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/net/can/kvaser_pciefd.c b/drivers/net/can/kvaser_pciefd.c
index a60d9efd5f8d..9ffc3ffb4e8f 100644
--- a/drivers/net/can/kvaser_pciefd.c
+++ b/drivers/net/can/kvaser_pciefd.c
@@ -1686,6 +1686,7 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
const struct kvaser_pciefd_irq_mask *irq_mask = pcie->driver_data->irq_mask;
u32 pci_irq = ioread32(KVASER_PCIEFD_PCI_IRQ_ADDR(pcie));
u32 srb_irq = 0;
+ u32 srb_release = 0;
int i;
if (!(pci_irq & irq_mask->all))
@@ -1699,17 +1700,14 @@ static irqreturn_t kvaser_pciefd_irq_handler(int irq, void *dev)
kvaser_pciefd_transmit_irq(pcie->can[i]);
}
- if (srb_irq & KVASER_PCIEFD_SRB_IRQ_DPD0) {
- /* Reset DMA buffer 0, may trigger new interrupt */
- iowrite32(KVASER_PCIEFD_SRB_CMD_RDB0,
- KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
- }
+ if (srb_irq & KVASER_PCIEFD_SRB_IRQ_DPD0)
+ srb_release |= KVASER_PCIEFD_SRB_CMD_RDB0;
- if (srb_irq & KVASER_PCIEFD_SRB_IRQ_DPD1) {
- /* Reset DMA buffer 1, may trigger new interrupt */
- iowrite32(KVASER_PCIEFD_SRB_CMD_RDB1,
- KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
- }
+ if (srb_irq & KVASER_PCIEFD_SRB_IRQ_DPD1)
+ srb_release |= KVASER_PCIEFD_SRB_CMD_RDB1;
+
+ if (srb_release)
+ iowrite32(srb_release, KVASER_PCIEFD_SRB_ADDR(pcie) + KVASER_PCIEFD_SRB_CMD_REG);
return IRQ_HANDLED;
}
--
2.43.0
