On 13.02.2024 11:22:49, Marc Kleine-Budde wrote: > On 12.01.2024 17:07:30, Srinivas Goud wrote: > > Add ECC feature support to Tx and Rx FIFOs for Xilinx CAN Controller. > > ECC is an IP configuration option where counter registers are added in > > IP for 1bit/2bit ECC errors count and reset. > > Also driver reports 1bit/2bit ECC errors for FIFOs based on ECC error > > interrupts. > > > > Add xlnx,has-ecc optional property for Xilinx AXI CAN controller > > to support ECC if the ECC block is enabled in the HW. > > > > Add ethtool stats interface for getting all the ECC errors information. > > > > There is no public documentation for it available. > > Lately I was using ethtool based stats, too and figured out, there's no > need for a spinlock, you can use a struct u64_stats_sync, > u64_stats_update_begin(), u64_stats_update_end(), and > u64_stats_fetch_retry() instead. These are no-ops on 64 bit systems and > sequential locks on 32 bit systems. > > I'll send a v8. https://lore.kernel.org/all/20240213-xilinx_ecc-v8-0-8d75f8b80771@xxxxxxxxxxxxxx/ Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung Nürnberg | Phone: +49-5121-206917-129 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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