Hi Rob, >-----Original Message----- >From: Rob Herring <robh@xxxxxxxxxx> >Sent: Monday, August 28, 2023 9:13 PM >To: Goud, Srinivas <srinivas.goud@xxxxxxx> >Cc: wg@xxxxxxxxxxxxxx; mkl@xxxxxxxxxxxxxx; davem@xxxxxxxxxxxxx; >edumazet@xxxxxxxxxx; kuba@xxxxxxxxxx; pabeni@xxxxxxxxxx; >krzysztof.kozlowski+dt@xxxxxxxxxx; conor+dt@xxxxxxxxxx; >p.zabel@xxxxxxxxxxxxxx; git (AMD-Xilinx) <git@xxxxxxx>; Simek, Michal ><michal.simek@xxxxxxx>; linux-can@xxxxxxxxxxxxxxx; linux-arm- >kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; >netdev@xxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx; >appana.durga.rao@xxxxxxxxxx; naga.sureshkumar.relli@xxxxxxxxxx >Subject: Re: [PATCH v3 1/3] dt-bindings: can: xilinx_can: Add ECC property >'xlnx,has-ecc' > >On Mon, Aug 28, 2023 at 08:28:43PM +0530, Srinivas Goud wrote: >> ECC feature added to Tx and Rx FIFOs for Xilinx AXI CAN Controller. >> Part of this feature configuration and counter registers added in IP >> for 1bit/2bit ECC errors. >> >> xlnx,has-ecc is optional property and added to Xilinx AXI CAN >> Controller node if ECC block enabled in the HW >> >> Signed-off-by: Srinivas Goud <srinivas.goud@xxxxxxx> >> --- >> Changes in v3: >> Update commit description >> >> Changes in v2: >> None > >Doesn't apply, dependency? This patch is created on top of below commit and this is part of the linux-can-next/master and Linux torvalds GIT https://lore.kernel.org/all/bfaed896cc51af02fe5f290675313ab4dcab0d33.1689164442.git.michal.simek@xxxxxxx/ > >> >> Documentation/devicetree/bindings/net/can/xilinx,can.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> index 64d57c3..c842610 100644 >> --- a/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> +++ b/Documentation/devicetree/bindings/net/can/xilinx,can.yaml >> @@ -49,6 +49,10 @@ properties: >> resets: >> maxItems: 1 >> >> + xlnx,has-ecc: >> + $ref: /schemas/types.yaml#/definitions/flag >> + description: CAN Tx and Rx fifo ECC enable flag (AXI CAN) > >has ECC or enable ECC? Will update description with "has ECC" > >> + >> required: >> - compatible >> - reg >> @@ -137,6 +141,7 @@ examples: >> interrupts = <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>; >> tx-fifo-depth = <0x40>; >> rx-fifo-depth = <0x40>; >> + xlnx,has-ecc > >Obviously not tested. Will fix it. Thanks, Srinivas
