On Wed. 10 May 2023 at 19:39, <Thomas.Kopp@xxxxxxxxxxxxx> wrote: > > > > > Re-reading the spec again I noticed that the part where I wrote > > > > > that there's an "idle condition" after the intermission is > > > > > wrong. What follows the intermission is just "bus idle", > > > > > defined two paragraphs later as "The period of bus idle may be > > > > > of arbitrary length." The 11 recessive bits can be removed from > > > > > the formula again. The longest period (under the assumption > > > > > there aren't multiple/continuous errors on the bus) will be > > > > > Frame + Error Frame (12 bit) + 2 x Overload Frame. > > > > ^^^^^^^^^^^^^^^^^^^^ > > > > > > > > How did you find that a error frame is 12 bits? From section 10.4.4 > > > > "Specification of EF", I can read: > > > > > > > > The EF shall consist of two different fields. The first field > > > > shall be given by the superposition of error flags contributed > > > > from different nodes. The second field shall be the error > > > > delimiter. > > > > > > > > Then: > > > > > > > > Two forms of error flag may be used, the active error flag and > > > > the passive error flag, where > > > > > > > > - the active error flag shall consist of 6 consecutive > > > > dominant bits, and > > > > > > > > - the passive error flag shall consist of 6 consecutive > > > > recessive bits unless it is overwritten by dominant bits > > > > from other nodes. > > > > > > > > Finally: > > > > > > > > The error delimiter shall consist of 8 recessive bits. > > > > > > > > So the error frame should be 14 bits (6 + 8), not 12, right? > > > That was imprecise, you're right - I meant an Error Flag, not Frame and hence > > the 8 recessive bits were missing. There's an active error flag + passive error > > flag though which can be 6 bits long each. In section 10.4.4.2 The total length > > of this sequence may vary between a minimum of 6 bit and a maximum of 12 > > bit. > > > > The active error flag and the passive error flag may both occur, but > > in that case, they occur as a superposition (c.f. above quotation). > > This also means that the passive error flag is seen if and only if all > > the nodes send a passive error flag. As long as one node sends an > > active error flag, the superposition will hide any other passive error > > flag. > > > > So, I think that the error flag is always 6. Actually, you were right on the total but not on the reasoning (active error flag + passive error flag 6 bits long each). The error flags are actually between 6 and 12 bits but not because of consecutive active and passive error flags. Even if the field is a superposition of error flags, the nodes do not necessarily start to transmit their error flag simultaneously on the same bit. The worst case is when node A sends an error flag, then node B detects the error condition on the last bit of A's error flag (bit #6). In that case, B starts to transmit his error flag after A's error flag is completed (bit #7) and B finishes sending its error frame on bit #12, thus the total of 6 + 6 = 12. But these may very well be all dominant bits! > I think if one node detects a bit error (that's not on the bus but inside the receiving node) on the second bit of the intermission it will start sending the 6 dominant bits, starting on the third bit of the intermission. Now, according to 10.4.2.2 " A node sampling a dominant bit during its suspend transmission time or at the third bit of intermission shall accept it as SOF.", treating the next 5 dominant bits as part of the ID of a new DF and only then sending its own error flag, giving a total of 12 dominant bits followed by 8 recessive bits EF delimiter etc. Am I missing something here? For this (I believe worst case when only considering 1 EF you could deduct one bittime - the third bit in the intermission) If a node detects a bit error on the second bit of the intermission, it means that it was expecting a recessive bit and measured a dominant one. Thus, it should interpret it as the beginning of an overload flag. Consequently, on the third bit of the intermission, that faulty node starts to emit an overload flag and according to paragraph 10.4.5.2, all the other nodes shall also start sending an overload flag. In fact, we could nearly say that an overload frame is an error frame sent during intermission. 10.4.6.2 "Intermission" clarifies this saying that: During the intermission [...] only signalling of overload condition is allowed. The disambiguation between error and overload can be done only because both can not coexist at the same time! ISO 11898-1 is such a rabbit hole... sights...
