Hi Marc, On Thu, Dec 01, 2022 at 05:59:53PM +0100, Markus Schneider-Pargmann wrote: > On Thu, Dec 01, 2022 at 12:00:33PM +0100, Marc Kleine-Budde wrote: > > On 01.12.2022 11:12:20, Markus Schneider-Pargmann wrote: > > > > > For the upcoming receive side patch I already added a hrtimer. I may try > > > > > to use the same timer for both directions as it is going to do the exact > > > > > same thing in both cases (call the interrupt routine). Of course that > > > > > depends on the details of the coalescing support. Any objections on > > > > > that? > > > > > > > > For the mcp251xfd I implemented the RX and TX coalescing independent of > > > > each other and made it configurable via ethtool's IRQ coalescing > > > > options. > > > > > > > > The hardware doesn't support any timeouts and only FIFO not empty, FIFO > > > > half full and FIFO full IRQs and the on chip RAM for mailboxes is rather > > > > limited. I think the mcan core has the same limitations. > > > > > > Yes and no, the mcan core provides watermark levels so it has more > > > options, but there is no hardware timer as well (at least I didn't see > > > anything usable). > > > > Are there any limitations to the water mark level? > > Anything specific? I can't really see any limitation. You can set the > watermark between 1 and 32. I guess we could also always use it instead > of the new-element interrupt, but I haven't tried that yet. That may > simplify the code. Just a quick comment here after trying this, I decided against it. - I can't modify the watermark levels once the chip is active. - Using interrupt (un)masking I can change the behavior for tx and rx with a single register write instead of two to the two fifo configuration registers. You will see this in the second part of the series then. Best, Markus
