Hi Biju,
On Sun, Jul 10, 2022 at 1:53 PM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> Add CAN binding documentation for Renesas RZ/N1 SoC.
>
> The SJA1000 CAN controller on RZ/N1 SoC has some differences compared
> to others like it has no clock divider register (CDR) support and it has
> no HW loopback (HW doesn't see tx messages on rx), so introduced a new
> compatible 'renesas,rzn1-sja1000' to handle these differences.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch, which is now commit 4591c760b7975984
("dt-bindings: can: nxp,sja1000: Document RZ/N1{D,S} in v6.0-rc1.
> --- a/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
> +++ b/Documentation/devicetree/bindings/net/can/nxp,sja1000.yaml
> @@ -11,9 +11,15 @@ maintainers:
>
> properties:
> compatible:
> - enum:
> - - nxp,sja1000
> - - technologic,sja1000
> + oneOf:
> + - enum:
> + - nxp,sja1000
> + - technologic,sja1000
> + - items:
> + - enum:
> + - renesas,r9a06g032-sja1000 # RZ/N1D
> + - renesas,r9a06g033-sja1000 # RZ/N1S
> + - const: renesas,rzn1-sja1000 # RZ/N1
>
> reg:
> maxItems: 1
> @@ -21,6 +27,9 @@ properties:
> interrupts:
> maxItems: 1
>
> + clocks:
> + maxItems: 1
> +
Probably you want to add the power-domains property, and make it
required on RZ/N1.
This is not super-critical, as your driver patch uses explicit clock
handling anyway.
> reg-io-width:
> $ref: /schemas/types.yaml#/definitions/uint32
> description: I/O register width (in bytes) implemented by this device
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
