I've added Michal Simek on into the loop. Michal can you figure out if there's an undocumented register to read the free running time stamp counter of the xilinx_can IP core? On 18.07.2022 12:40:03, Matej Vasilevski wrote: > On Mon, Jul 18, 2022 at 10:33:12AM +0200, Marc Kleine-Budde wrote: > > On 16.07.2022 14:04:09, Matej Vasilevski wrote: > > > This patch adds support for hardware RX timestamps from Xilinx Zynq CAN > > > controllers. The timestamp is calculated against a timepoint reference > > > stored when the first CAN message is received. > > > > > > When CAN bus traffic does not contain long idle pauses (so that > > > the clocks would drift by a multiple of the counter rollover time), > > > then the hardware timestamps provide precise relative time between > > > received messages. This can be used e.g. for latency testing. > > > > Please make use of the existing cyclecounter/timecounter framework. Is > > there a way to read the current time from a register? If so, please > > setup a worker that does that regularly. > > > > Have a look at the mcp251xfd driver as an example: > > > > https://elixir.bootlin.com/linux/latest/source/drivers/net/can/spi/mcp251xfd/mcp251xfd-timestamp.c > > Hi Marc, > > as Pavel have said, the counter register isn't readable. Some HW designer successfully ticked the mark [x] HW time stamp support! But haven't thought on how to use this. No Overflow IRQ and no possibility to read the free running timer. :/ > I'll try to fit the timecounter/cyclecounter framework and send a v2 > patch if it works well. Thanks for the suggestion, it didn't occur to me > that I can use it in this case as well. Maybe it's possible to add the ktimestamp based overflow calculation there, too. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung West/Dortmund | Phone: +49-231-2826-924 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Attachment:
signature.asc
Description: PGP signature
