Hi Marc, Thanks for the feedback. > Subject: Re: [PATCH v4 6/6] can: sja1000: Add support for RZ/N1 SJA1000 > CAN Controller > > On 10.07.2022 12:52:48, Biju Das wrote: > > The SJA1000 CAN controller on RZ/N1 SoC has no clock divider register > > (CDR) support compared to others. > > > > This patch adds support for RZ/N1 SJA1000 CAN Controller, by adding > > SoC specific compatible to handle this difference as well as using clk > > framework to retrieve the CAN clock frequency. > > > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > > --- > > v3->v4: > > * Updated commit description. > > * Updated clock handling as per bindings. > > v2->v3: > > * No change. > > v1->v2: > > * Updated commit description as SJA1000_NO_HW_LOOPBACK_QUIRK is > > removed > > * Added error handling on clk error path > > * Started using "devm_clk_get_optional_enabled" for clk get,prepare > and enable. > > Due to the use of the devm_clk_get_optional_enabled(), this patch has to > wait until devm_clk_get_optional_enabled() hits net-next/master, which > will be probably for the v5.21 merge window. OK, will wait for 5.21 merge window, as this driver is the first user for this API. Cheers, Biju
