On 25/06/2022 13:03, Marc Kleine-Budde wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > PolarFire SoC has a pair of CAN controllers, but as they were > undocumented there were omitted from the device tree. Add them. > > Link: https://lore.kernel.org/all/20220607065459.2035746-3-conor.dooley@xxxxxxxxxxxxx > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Signed-off-by: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx> Hey Marc, Not entirely familiar with the process here. Do I apply this patch when the rest of the series gets taken, or will this patch go through the net tree? Thanks, Conor. > --- > arch/riscv/boot/dts/microchip/mpfs.dtsi | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi > index 8c3259134194..737e0e70c432 100644 > --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi > +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi > @@ -330,6 +330,24 @@ i2c1: i2c@2010b000 { > status = "disabled"; > }; > > + can0: can@2010c000 { > + compatible = "microchip,mpfs-can"; > + reg = <0x0 0x2010c000 0x0 0x1000>; > + clocks = <&clkcfg CLK_CAN0>; > + interrupt-parent = <&plic>; > + interrupts = <56>; > + status = "disabled"; > + }; > + > + can1: can@2010d000 { > + compatible = "microchip,mpfs-can"; > + reg = <0x0 0x2010d000 0x0 0x1000>; > + clocks = <&clkcfg CLK_CAN1>; > + interrupt-parent = <&plic>; > + interrupts = <57>; > + status = "disabled"; > + }; > + > mac0: ethernet@20110000 { > compatible = "cdns,macb"; > reg = <0x0 0x20110000 0x0 0x2000>; > -- > 2.35.1 > >
