This patch actually changes the order of the TX and RX FIFOs. This gives the opportunity to minimize the number of SPI transfers in the IRQ handler. The read of the IRQ status register and RX FIFO status registers can be combined into single SPI transfer. If the RX ring uses FIFO 1, the overall length of the transfer is smaller than in the original layout, where the RX FIFO comes after the TX FIFO. Link: https://lore.kernel.org/all/20220217103826.2299157-5-mkl@xxxxxxxxxxxxxx Signed-off-by: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx> --- drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c | 2 +- drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c index 39005725c665..9657dbf251b0 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-ring.c @@ -215,8 +215,8 @@ void mcp251xfd_ring_init(struct mcp251xfd_priv *priv) netdev_reset_queue(priv->ndev); mcp251xfd_ring_init_tef(priv, &base); - mcp251xfd_ring_init_tx(priv, &base, &fifo_nr); mcp251xfd_ring_init_rx(priv, &base, &fifo_nr); + mcp251xfd_ring_init_tx(priv, &base, &fifo_nr); } void mcp251xfd_ring_free(struct mcp251xfd_priv *priv) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h index 5c3f7f25caf0..8ee959890aea 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -596,8 +596,8 @@ struct mcp251xfd_priv { u32 spi_max_speed_hz_slow; struct mcp251xfd_tef_ring tef[1]; - struct mcp251xfd_tx_ring tx[1]; struct mcp251xfd_rx_ring *rx[1]; + struct mcp251xfd_tx_ring tx[1]; u8 rx_ring_num; -- 2.34.1
