Hi all,
On 20/09/21 5:56 pm, Aswath Govindraju wrote:
> The read an writes from the fifo are from a buffer with various fields and
> data at predefined offsets. So, they reads and writes should not be done to
> the same address(or port) in case of val_count greater than 1. Therefore,
> fix this by using iowrite32/ioread32 instead of ioread32_rep/iowrite32_rep.
>
> Also, the write into fifo must be performed with an offset from the message
> ram base address. Therefore, fix the base address to mram_base.
>
> Fixes: e39381770ec9 ("can: m_can: Disable IRQs on FIFO bus errors")
> Signed-off-by: Aswath Govindraju <a-govindraju@xxxxxx>
> ---
Please ignore this patch sent it my mistake. Sorry for the inconvenience.
Thanks,
Aswath
> drivers/net/can/m_can/m_can_platform.c | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c
> index 308d4f2fff00..eee47bad0592 100644
> --- a/drivers/net/can/m_can/m_can_platform.c
> +++ b/drivers/net/can/m_can/m_can_platform.c
> @@ -32,8 +32,13 @@ static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
> static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
> {
> struct m_can_plat_priv *priv = cdev_to_priv(cdev);
> + void __iomem *src = priv->mram_base + offset;
>
> - ioread32_rep(priv->mram_base + offset, val, val_count);
> + while (val_count--) {
> + *(unsigned int *)val = ioread32(src);
> + val += 4;
> + src += 4;
> + }
>
> return 0;
> }
> @@ -51,8 +56,13 @@ static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
> const void *val, size_t val_count)
> {
> struct m_can_plat_priv *priv = cdev_to_priv(cdev);
> + void __iomem *dst = priv->mram_base + offset;
>
> - iowrite32_rep(priv->base + offset, val, val_count);
> + while (val_count--) {
> + iowrite32(*(unsigned int *)val, dst);
> + val += 4;
> + dst += 4;
> + }
>
> return 0;
> }
>
