[PATCH] dt-bindings: clock: imx5: fix example

[Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>]

Since commit:

    0e030a373df3 ("can: flexcan: fix endianess detection")

the fsl,imx53-flexcan isn't compatible with the fsl,p1010-flexcan any more. As
the former accesses the IP core in Little Endian mode and the latter uses Big
Endian mode.

With the conversion of the flexcan DT bindings to yaml, the dt_binding_check
this throws the following error:

Documentation/devicetree/bindings/clock/imx5-clock.example.dt.yaml: can@53fc8000: compatible: 'oneOf' conditional failed, one must be fixed:
        ['fsl,imx53-flexcan', 'fsl,imx25-flexcan'] is too long
        Additional items are not allowed ('fsl,imx25-flexcan' was unexpected)
        'fsl,imx53-flexcan' is not one of ['fsl,imx7d-flexcan', 'fsl,imx6ul-flexcan', 'fsl,imx6sx-flexcan']
        'fsl,imx53-flexcan' is not one of ['fsl,ls1028ar1-flexcan']
        'fsl,imx6q-flexcan' was expected
        'fsl,lx2160ar1-flexcan' was expected
        From schema: Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml

The error is fixed by removing the "fsl,p1010-flexcan" compatible (which turned
out the be incompatible) from the binding example.

Cc: Fabio Estevam <fabio.estevam@xxxxxxx>
Cc: devicetree@xxxxxxxxxxxxxxx
Reported-by: Rob Herring <robh+dt@xxxxxxxxxx>
Signed-off-by: Marc Kleine-Budde <mkl@xxxxxxxxxxxxxx>
---
 Documentation/devicetree/bindings/clock/imx5-clock.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/imx5-clock.yaml b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
index 4d9e7c73dce9..155379c3c41e 100644
--- a/Documentation/devicetree/bindings/clock/imx5-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/imx5-clock.yaml
@@ -57,7 +57,7 @@ examples:
     };
 
     can@53fc8000 {
-        compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+        compatible = "fsl,imx53-flexcan";
         reg = <0x53fc8000 0x4000>;
         interrupts = <82>;
         clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
-- 
2.28.0