This is my first post to the list, so please inform me of any errors in
etiquette.
I'm evaluating the MCP2518FD, and have two questions to the driver.
1. I could not find any references to the GPIOs of the chip. Is it
correct that these are not exposed to the host system?
2. When setting the oscillator frequency outside the
MCP25XXFD_SYSCLOCK_HZ_MIN and MCP25XXFD_SYSCLOCK_HZ_MAX range, the
frequency is compared to the max value scaled by the max PLL value. Is
the intention to compare with the min value? Currently, an external
oscillator of 4 MHz and a PLL value of 10, resulting in 40 MHz, is
treated as being too low.
diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c
b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c
index bd2ba981ae36..9e0246c4e49f 100644
--- a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c
+++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c
@@ -2770,7 +2770,7 @@ static int mcp25xxfd_probe(struct spi_device *spi)
return -ERANGE;
}
- if (freq <= MCP25XXFD_SYSCLOCK_HZ_MAX / MCP25XXFD_OSC_PLL_MULTIPLIER) {
+ if (freq <= MCP25XXFD_SYSCLOCK_HZ_MIN / MCP25XXFD_OSC_PLL_MULTIPLIER) {
dev_err(&spi->dev,
"Oscillator frequency (%u Hz) is too low and PLL is not
supported.\n",
freq);
Regards, Magnus.
