On 9/16/20 12:08 PM, Thomas Kopp wrote: > Signed-off-by: Thomas Kopp <thomas.kopp@xxxxxxxxxxxxx> > --- > drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c > index 6ffa7af50119..670b7d1e1f46 100644 > --- a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c > +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd-core.c > @@ -2821,11 +2821,13 @@ static int mcp25xxfd_probe(struct spi_device *spi) > * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 18750000 Hz 93.75% 600000000 Hz bad assigned-clocks = <&ccu CLK_SPIx> > * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 9090909 Hz 90.09% 18181819 Hz good assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> > * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 9523809 Hz 95.34% 28571429 Hz bad assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> > + * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82% 82000000 Hz good default > + * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82% 82000000 Hz good default > * > - * Limit SPI clock to 92.5% of SYSCLOCK / 2 for now. > + * Limit SPI clock to 85% of SYSCLOCK / 2 for now. > */ > priv->spi_max_speed_hz_orig = spi->max_speed_hz; > - spi->max_speed_hz = min(spi->max_speed_hz, freq / 2 / 1000 * 925); > + spi->max_speed_hz = min(spi->max_speed_hz, freq / 2 / 1000 * 850); > spi->bits_per_word = 8; > spi->rt = true; > err = spi_setup(spi); > Squashed into the "can: mcp25xxfd: add driver for Microchip MCP25xxFD SPI CAN" patch. thanks, Marc -- Pengutronix e.K. | Marc Kleine-Budde | Embedded Linux | https://www.pengutronix.de | Vertretung West/Dortmund | Phone: +49-231-2826-924 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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