On 08/20/2018 12:10 PM, Pankaj Bansal wrote: > In Flexcan CAN_CTRL[LPB] bit description: > > NOTE: In this mode, the CAN_MCR[SRXDIS] cannot be asserted because this > will impede the self > reception of a transmitted message. > > this is true for all versions of Flexcan cores, old or new. Ok - I cannot find this in my IMX6DQRM Rev. 5, 06/2018. It says: >> This bit configures FlexCAN to operate in Loop-Back Mode. In this mode, FlexCAN performs an internal >> loop back that can be used for self test operation. The bit stream output of the transmitter is fed back >> internally to the receiver input. The FLEXCAN_RX input pin is ignored and the FLEXCAN_TX output goes >> to the recessive state (logic '1'). FlexCAN behaves as it normally does when transmitting, and treats its >> own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the >> bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to >> ensure proper reception of its own message. Both transmit and receive interrupts are generated. This bit >> can only be written in Freeze mode as it is blocked by hardware in other modes. >> Loop Back enabled >> Loop Back disabled Can you add comment that the self reception bit is needed for loopback mode, but not documented. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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