On Thu, 2018-10-18 at 21:18 +-0800, Ming Lei wrote:
+AD4 Turns out q-+AD4-dma+AF8-alignement should be stack limit because now bvec table
+AF4AXgBeAF4AXgBeAF4AXgBeAF4AXgBeAF4AXg
dma+AF8-alignment?
+AD4 is immutalbe, the underlying queue's dma alignment has to be perceptible
+AF4AXgBeAF4AXgBeAF4AXgBe +AF4AXgBeAF4AXgBeAF4AXgBeAF4AXg
immutable? observable?
+AD4 by stack driver, so IO buffer can be allocated as dma aligned before
+AF4AXgBeAF4AXg
stacked?
Anyway:
Reviewed-by: Bart Van Assche +ADw-bvanassche+AEA-acm.org+AD4
