Karl Hammar wrote: > Folderol: >> karl@xxxxxxxxxxx (Karl Hammar) wrote: >>> Folderol: > ... >>>> For rough testing it could be used to lock a pair of ADCs. TLC4545ID >>>> looks like a good (cheap) possibility here. >>> Found it, datasheet at [1], it seems to cost ~12USD. There is no >>> "start" pin to be able to simultaneously start multiple converters. >>> And you cannot daisychain this chip. [2] can be daisy-chained, but >>> with a maximum of eigth channels, but it can be synced. >> There is a chip select feature, > > The chip select comes with the spi bus interface, which(s) chip shall > respond to the clock. > >> and also a count overrun, both of which >> put the output into high Z state. Therefore the outputs can be >> paralleled, and count pulses sent to the appropriate chips by the >> processor. > > That is normal for chips with spi bus. > >> It also has an interesting feature of having it's own high >> speed conversion clock, > > Some has an internal clock and some need an external. At most this will > affect component count. > >> so presumably, once a conversion has been >> done you can read the result at your leisure - not sure how this would >> actually work. I hadn't read far enough to find out if/how this could >> be synced. > > It doesn't seem to be an easy way to sync TLC4545ID's. The sampling > start after 5 clcks after chip_select, it need another 20 clcks for the > sampling. Then you release the chip and it will convert the analog value > to digital and it takes < 2.94us. During the sampling time the previous > is clocked out. > > That is why I'm looking for a "start" pin on the chip, to be able to > say to all ADCs to start simultaneously. > >>> If we are going to have multiple analog inputs at higt sample rate, >>> isn't it better to have a parallell interface. With spi the number of >>> channels will be limited to something like 8 for a 24bit converter. >>> Plus that the AT32AP7000/AT91SAM9260 only has two spi-busses. >>> >>> Maybe ad7762 [2] could be useful (28 USD), >> Not sure how you'd effectively squeeze in multiple channels of 24 bits >> parallel without quite a lot of juggling. > > Do we understand each other correctly? > > With a parallell bus I mean a bus with multiple data lines and multiple > address lines. Examples of parallell buses are ISA and PCI. > Another way to do that would be to bit-bang 8 SPI devices sharing one clock line (and /CS/FS) onto a byte-wide port, read all 8 in parallel one bit at a time in perfect sync. It actually should be possible to use a /RD line for an SPI clock, so 24 successive reads of a single address would clock in 8 24-bit samples. Martin _______________________________________________ Linux-audio-user mailing list Linux-audio-user@xxxxxxxxxxxxxxxxxxxx http://lists.linuxaudio.org/mailman/listinfo/linux-audio-user
