Mark Knecht wrote: > I asked some questions about this of the Linux kernel developers in > September of 2002. I received a couple of pretty informative answers. > ... > The problems I had with these explanations was that they didn't clarify > the routing of physical interrupt lines to the order of the vector tables. The interrupt controller in the chipset (the I/O-APIC) has several PCI interrupt inputs, named PIRQA, PIRQB, etc. The motherboard manual should explain how the interrupt lines of AGP/PCI cards and onboard chips are routed to these inputs. (Please note that the table in the P4P800's manual is partly wrong.) When not in APIC mode, each PIRQx input can be mapped to one of the 16 ISA interrupts. When in APIC mode, there is a fixed mapping of PIRQx inputs to interrupts above 15 (PIRQA = 16, PIRQB = 17, ...). Each of these 16 or 24+ hardware interrupts can be routed to one of 256 software interrupt vectors. > In motherboard design, the layout of the interrupt lines may > possibly be a single line between two or more devices. [...] Since > they share the same physical line they have to be shared, but this > discussion didn't clear up for me how that's done. It's a simple electrical connection. PCI interrupts are active-low, level-triggered, so the I/O-APIC will see an active interrupt line if any of the devices requests an interrupt. If multiple PIRQx inputs are mapped to the same interrupt number, that's an additional level of sharing. > The devices go into their own vector even if they are shared. > (AFAICT) This is not the case. If devices share a PIRQx input, they must share the software interrupt, too. > Also, the first link says 'For APICs, when two interrupts are present > when interrupts are enabled, the one with the highest interrupt vector > number will be taken first' and 'So, the last PCI interrupt source in the > MPS table will be the highest priority'. > > However the second link says 'The local APIC unit will handle interrupts > depending on vector, with lowest being highest priority. Here is a sample > table with NR being the IRQ e.g. 0 = 31;' > > For me this wording seems contradictory, I think the first is simply wrong (but MPS isn't used on a modern ACPI system anyway.) The table shown by Zwane is output into the system log when booting. (IIRC vector numbers are assigned in increments of 8 because some APIC uses groups of 16 numbers when determining interrupt priorities.) > One other piece of interesting information was that you can supposedly > control the ordering of the interrupt table using some kernel type software. > This would be quite cool since you could then insert your sound card > anywhere into the list and give it the very best servicing that your machine > can provide. The "Task Priority Register" register mentioned there lets you assign a priority to each CPU, so that an interrupt can interrupt the lowest-priority task in a multi-CPU system. Intel says the TPR shouldn't be used with the P4 (probably because the time needed for arbitration between the CPUs is rather long). Regards, Clemens
