On Thu, 7 Apr 2016 01:57:07 +0200 Robin Gareus <robin@xxxxxxxxxx> wrote: > How would that effectively differ from running at twice the > buffersize? > > That approach just moves the load to two CPU cores. If those two cores > can produce the result in a given time, a single core can do the same > with twice the buffersize. Identical total latency. With twice the buffer size, one core has twice as much work to do in twice as much time, which basically doesn't change the DSP load (but there are less context switches, etc.) With a decoupling buffer between stages of the pipeline, the load is spread on cores, so DSP load is theoretically halved. I agree that from the user point of view, latency is doubled as if buffer size would have been doubled, but more DSP power is available. -a.
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