On Mon, Dec 06, 2021 at 01:48:12PM +0000, Marc Zyngier wrote:
> > > > +static int qcom_mpm_enter_sleep(struct qcom_mpm_priv *priv)
> > > > +{
> > > > + int i, ret;
> > > > +
> > > > + for (i = 0; i < priv->reg_stride; i++)
> > > > + qcom_mpm_write(priv, MPM_REG_STATUS, i, 0);
> > > > +
> > > > + /* Notify RPM to write vMPM into HW */
> > >
> > > What do you mean by 'into HW'? We just did that, right? or are these
> > > registers just fake and most of the stuff is in the RPM?
> >
> > I have a note about this in commit log.
> >
> > - All the register settings are done by APSS on an internal memory
> > region called vMPM, and RPM will flush them into hardware after it
> > receives a mailbox/IPC notification from APSS.
> >
> > So yes, these registers are fake/virtual in memory, and RPM will
> > actually flush the values into the MPM hardware block.
>
> Then why are you using MMIO accessors all over the place if this is
> just RAM? Who *owns* this memory? Is it normal DRAM? Or some flops
> exposed by a device? Why isn't the state simply communicated over the
> mailbox instead?
It's a piece of internal memory (SRAM) which can be access by AP and
RPM. The communication mechanism is defined by SoC/RPM design, and we
can do nothing but following the procedure.
Shawn
