Quoting Stephen Boyd (2021-10-21 11:06:53)
> Quoting Prasad Malisetty (2021-10-14 11:06:24)
> > Add pcie clock phandle for sc7280 SoC and correct
> > The pcie_1_pipe-clk clock name as same as binding.
> >
> > fix: ab7772de8 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
>
> This is wrong. Should be
>
> Fixes: ab7772de8612 ("arm64: dts: qcom: SC7280: Add rpmhcc clock controller node")
>
> > Signed-off-by: Prasad Malisetty <pmaliset@xxxxxxxxxxxxxx>
> > Reported-by: kernel test robot <lkp@xxxxxxxxx>
> >
> > ---
> > This change is depends on the below patch series.
> > https://lkml.org/lkml/2021/10/7/841
>
> Why doesn't that patch update this clock cell then?
Looks like Bjorn already picked it up so that answers my question.
>
> > ---
> > arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 39635da..78694c1 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -569,9 +569,10 @@
> > reg = <0 0x00100000 0 0x1f0000>;
> > clocks = <&rpmhcc RPMH_CXO_CLK>,
> > <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> > - <0>, <0>, <0>, <0>, <0>, <0>;
> > + <0>, <&pcie1_lane 0>,
> > + <0>, <0>, <0>, <0>;
> > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> > - "pcie_0_pipe_clk", "pcie_1_pipe-clk",
> > + "pcie_0_pipe_clk", "pcie_1_pipe_clk",
>
> This can be split from the patch to fix just the name in one patch and
> then add the pcie1_lane phandle in the next patch. That way new features
> aren't being mixed together with the string fix.
>
In addition, I see that Rob sent a patch[1] that fixes the interrupt-map
in the pcie node. Can you send a similar patch for sc7280? It looks
wrong. We need another two zeroes like on sdm845.dtsi. So please resend
this series with three patches and the appropriate Fixes tags.
[1] https://lore.kernel.org/r/20210928192210.1842377-1-robh@xxxxxxxxxx
