On 30-07-21, 01:15, Dmitry Baryshkov wrote:
> On 15/07/2021 09:51, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > index 2d4645e01ebf..aeea6add61ee 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > @@ -25,6 +25,8 @@
> > #define CTL_MERGE_3D_ACTIVE 0x0E4
> > #define CTL_INTF_ACTIVE 0x0F4
> > #define CTL_MERGE_3D_FLUSH 0x100
> > +#define CTL_DSC_ACTIVE 0x0E8
> > +#define CTL_DSC_FLUSH 0x104
> > #define CTL_INTF_FLUSH 0x110
> > #define CTL_INTF_MASTER 0x134
> > #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> > @@ -34,6 +36,7 @@
> > #define DPU_REG_RESET_TIMEOUT_US 2000
> > #define MERGE_3D_IDX 23
> > +#define DSC_IDX 22
> > #define INTF_IDX 31
> > #define CTL_INVALID_BIT 0xffff
> > @@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
> > static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> > {
> > + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3));
>
> Please pass DSC indices using intf cfg and use them to configure register
> writes.
Yes I have modified the intf cfg dsc from bool to pass actual indices.
So this patch goes next (as a dependency reorder) and we use this only
when DSC is enabled and use the indices set. Thanks for the suggestion
--
~Vinod
