Hi, On Sun, Sep 5, 2021 at 8:20 PM Sibi Sankar <sibis@xxxxxxxxxxxxxx> wrote: > > On 2021-08-31 22:34, Bjorn Andersson wrote: > > On Tue 31 Aug 08:30 PDT 2021, Matthias Kaehlcke wrote: > > > >> On Thu, Jul 29, 2021 at 11:34:44PM +0530, Sibi Sankar wrote: > >> > Fixup the register regions used by the cpufreq node on SC7280 SoC to > >> > support per core L3 DCVS. > >> > > >> > Fixes: 7dbd121a2c58 ("arm64: dts: qcom: sc7280: Add cpufreq hw node") > >> > Signed-off-by: Sibi Sankar <sibis@xxxxxxxxxxxxxx> > >> > >> This patch landed in the Bjorn's tree, however the corresponding > >> driver > >> change ("cpufreq: qcom: Re-arrange register offsets to support per > >> core > >> L3 DCVS" / > >> https://patchwork.kernel.org/project/linux-arm-msm/patch/1627581885-32165-3-git-send-email-sibis@xxxxxxxxxxxxxx/) > >> did not land in any maintainer tree yet AFAIK. IIUC the DT change > >> alone > >> breaks cpufreq since the changed register regions require the changed > >> offset in the cpufreq driver. > >> > > > > Thanks for the note Matthias, it must have slipped by as I scraped the > > inbox for things that looked ready. > > > > I'm actually not in favor of splitting these memory blocks in DT to > > facilitate the Linux implementation of splitting that in multiple > > drivers... > > > > But I've not been following up on that discussion. > > > > Regards, > > Bjorn > > > >> Sibi, please confirm or clarify that my concern is unwarranted. > > Let's drop the patch asap as it breaks > SC7280 cpufreq on lnext without the driver > changes. It's already landed so we need a revert: https://lore.kernel.org/r/20210907121220.1.I08460f490473b70de0d768db45f030a4d5c17828@changeid/ -Doug