On Fri 03 Sep 11:09 PDT 2021, AngeloGioacchino Del Regno wrote: > All smartphones of this platform are equipped with a WCD9335 audio > codec, getting its MCLK from PM8998 gpio13: add this clock to DT. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> > Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> > --- > .../dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > index 5fbe5abf4133..7aeebd3b2e9e 100644 > --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi > @@ -20,6 +20,19 @@ / { > qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ > qcom,board-id = <8 0>; > > + clocks { > + compatible = "simple-bus"; > + > + div1_mclk: divclk1 { > + compatible = "gpio-gate-clock"; > + pinctrl-0 = <&audio_mclk_pin>; > + pinctrl-names = "default"; > + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; What controls the clock rate of divclk1? Regards, Bjorn > + #clock-cells = <0>; > + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > board_vbat: vbat-regulator { > compatible = "regulator-fixed"; > regulator-name = "VBAT"; > @@ -313,6 +326,12 @@ cam_snapshot_pin_a: cam-snapshot-btn-active { > input-enable; > qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; > }; > + > + audio_mclk_pin: audio-mclk-pin-active { > + pins = "gpio13"; > + function = "func2"; > + power-source = <0>; > + }; > }; > > &pmi8998_gpio { > -- > 2.32.0 >