On Sun, 29 Aug 2021 at 23:30, Marijn Suijten
<marijn.suijten@xxxxxxxxxxxxxx> wrote:
>
> The 28NM DSI PLL driver for msm8960 calculates with a 27MHz reference
> clock and should hence use PXO, not CXO which runs at 19.2MHz.
>
> Note that none of the DSI PHY/PLL drivers currently use this "ref"
> clock; they all rely on (sometimes inexistant) global clock names and
> usually function normally without a parent clock. This discrepancy will
> be corrected in a future patch, for which this change needs to be in
> place first.
>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Checked the downstream driver, it always uses 27 MHz clock in calculations.
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 2687c4e890ba..77659b783759 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -198,7 +198,7 @@ cxo_board: cxo_board {
> clock-frequency = <19200000>;
> };
>
> - pxo_board {
> + pxo_board: pxo_board {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <27000000>;
> @@ -1306,7 +1306,7 @@ dsi0_phy: dsi-phy@4700200 {
> reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
> clock-names = "iface_clk", "ref";
> clocks = <&mmcc DSI_M_AHB_CLK>,
> - <&cxo_board>;
> + <&pxo_board>;
> };
>
>
> --
> 2.33.0
>
--
With best wishes
Dmitry
