On Sun, 29 Aug 2021 at 06:51, Stephen Boyd <sboyd@xxxxxxxxxx> wrote: > > Quoting Dmitry Baryshkov (2021-08-26 14:56:23) > > On 26/08/2021 21:31, Stephen Boyd wrote: > > > Quoting Dmitry Baryshkov (2021-07-27 13:19:56) > > >> On SM8250 both the display and video clock controllers are powered up by > > >> the MMCX power domain. Handle this by linking clock controllers to the > > >> proper power domain, and using runtime power management to enable and > > >> disable the MMCX power domain. > > >> > > >> Dependencies: > > >> - https://lore.kernel.org/linux-arm-msm/20210703005416.2668319-1-bjorn.andersson@xxxxxxxxxx/ > > >> (pending) > > > > > > Does this patch series need to go through the qcom tree? Presumably the > > > dependency is going through qcom -> arm-soc > > > > It looks like Bjorn did not apply his patches in the for-5.15 series, so > > we'd have to wait anyway. Probably I should rebase these patches instead > > on Rajendra's required-opps patch (which is going in this window). > > > > Ok. Thanks. I'll drop it from my queue for now. Just for the reference. I've sent v7 of this patchset. After thinking more about power domains relationship, I think we have a hole in the abstraction here. Currently subdomains cause power domains to be powered up, but do not dictate the performance level the parent domain should be working in. While this does not look like an issue for the gdsc (and thus it can be easily solved by the Bjorn's patches, which enforce rpmhpd to be powered on to 'at least lowest possible' performance state, this might be not the case for the future links. I think at some point the pd_add_subdomain() interface should be extended with the ability to specify minimum required performance state when the link becomes on. Until that time I have changed code to enforce having clock controller in pm resume state when gdsc is enabled, thus CC itself votes on parent's (rpmhpd) performance state. -- With best wishes Dmitry
