In subject: s/add support/Add support/ to match previous history. On Wed, May 05, 2021 at 12:18:30PM +0300, Baruch Siach wrote: > From: Selvam Sathappan Periakaruppan <speriaka@xxxxxxxxxxxxxx> > > IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that > platform. > > The code is based on downstream Codeaurora kernel v5.4. Split out the > DBI registers access part from .init into .post_init. DBI registers are > only accessible after phy_power_on(). The "downstream Codeaurora kernel v5.4" reference would be more useful if there were a URL reference to that driver. > +#define AXI_CLK_RATE 200000000 > +#define RCHNG_CLK_RATE 100000000 These are unused. > + for (i = 0;i < 256;i++) Add spaces after semicolons.
