Hi, Baruch Siach <baruch@xxxxxxxxxx> writes: > Hi Felipe, > > On Wed, Aug 04 2021, Felipe Balbi wrote: >> Baruch Siach <baruch@xxxxxxxxxx> writes: >>> @@ -1371,6 +1398,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) >>> &dwc->hsphy_interface); >>> device_property_read_u32(dev, "snps,quirk-frame-length-adjustment", >>> &dwc->fladj); >>> + device_property_read_u32(dev, "snps,ref-clock-period", >>> + &dwc->ref_clk_per); >> >> I wonder if it would make more sense to pass an actual clock reference >> here. If valid, then reconfigure the period to the value returned by >> clk_get_rate(). It would avoid yet another DT binding. If we make the >> clock optional, then we won't affect any other platforms. The clock >> itself could be a regular fixed clock node. > > Thinh Nguyen asked to add a dedicated DT property. He explained that > clk_get_rate() does not work for PCI hosted dwc3. This is the most > complete summary of the discussion: Hence the "optional" :-) Or, perhaps, Thinh wants to use this for internal FPGA-based validation? In that case, I'm okay with the property. -- balbi
