On 6/29/21 9:04 PM, Abhinav Kumar wrote:
During board bringups its useful to have a DSI test pattern
generator to isolate a DPU vs a DSI issue and focus on the relevant
hardware block.
To facilitate this, add an API which triggers the DSI controller
test pattern. The expected output is a rectangular checkered pattern.
This has been validated on a single DSI video mode panel by calling it
right after drm_panel_enable() which is also the ideal location to use
this as the DSI host and the panel have been initialized by then.
Further validation on dual DSI and command mode panel is pending.
If there are any fix ups needed for those, it shall be applied on top
of this change.
Signed-off-by: Abhinav Kumar <abhinavk@xxxxxxxxxxxxxx>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Tested-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
[...]
+static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
+{
+ u32 reg;
+
+ reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
+
+ dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
+
+ reg |= (0x3 << 0x8);
+ dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
+ /* draw checkered rectangle pattern */
+ dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, (0x1 << 0x7));
How about BIT(7)?
On SM6125 this seems to change the color intensity of the pattern; it is
always colored lines of a few pixels wide alternating R, B and G from
left to right. Is it possible to document the meaning and available
values of these registers, especially if they differ between SoC / DSI
block?
Kind regards,
Marijn
+ DBG("Cmd test pattern setup done\n");
+}
[...]
