Add device tree bindings for video clock controller for SM8350 SoCs.
Signed-off-by: Robert Foss <robert.foss@xxxxxxxxxx>
---
.../bindings/clock/qcom,videocc.yaml | 2 +
.../dt-bindings/clock/qcom,videocc-sm8350.h | 44 +++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8350.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index 567202942b88..a1dfecbad5c9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -18,6 +18,7 @@ description: |
dt-bindings/clock/qcom,videocc-sdm845.h
dt-bindings/clock/qcom,videocc-sm8150.h
dt-bindings/clock/qcom,videocc-sm8250.h
+ dt-bindings/clock/qcom,videocc-sm8350.h
properties:
compatible:
@@ -26,6 +27,7 @@ properties:
- qcom,sdm845-videocc
- qcom,sm8150-videocc
- qcom,sm8250-videocc
+ - qcom,sm8350-videocc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8350.h b/include/dt-bindings/clock/qcom,videocc-sm8350.h
new file mode 100644
index 000000000000..531cad2b0ab5
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8350.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8350_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK 0
+#define VIDEO_CC_AHB_CLK_SRC 1
+#define VIDEO_CC_MVS0_CLK 2
+#define VIDEO_CC_MVS0_CLK_SRC 3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
+#define VIDEO_CC_MVS0C_CLK 5
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6
+#define VIDEO_CC_MVS1_CLK 7
+#define VIDEO_CC_MVS1_CLK_SRC 8
+#define VIDEO_CC_MVS1_DIV2_CLK 9
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 10
+#define VIDEO_CC_MVS1C_CLK 11
+#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 12
+#define VIDEO_CC_SLEEP_CLK 13
+#define VIDEO_CC_SLEEP_CLK_SRC 14
+#define VIDEO_CC_XO_CLK 15
+#define VIDEO_CC_XO_CLK_SRC 16
+#define VIDEO_PLL0 17
+#define VIDEO_PLL1 18
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_CVP_INTERFACE_BCR 0
+#define VIDEO_CC_CVP_MVS0_BCR 1
+#define VIDEO_CC_MVS0C_CLK_ARES 2
+#define VIDEO_CC_CVP_MVS0C_BCR 3
+#define VIDEO_CC_CVP_MVS1_BCR 4
+#define VIDEO_CC_MVS1C_CLK_ARES 5
+#define VIDEO_CC_CVP_MVS1C_BCR 6
+
+#define MVS0C_GDSC 0
+#define MVS1C_GDSC 1
+#define MVS0_GDSC 2
+#define MVS1_GDSC 3
+
+#endif
--
2.30.2
