Re: [PATCH V3 1/3] arm64: dts: sc7280: Add QSPI node

[rojay@xxxxxxxxxxxxxx]

On 2021-06-06 09:25, Bjorn Andersson wrote:
> On Fri 04 Jun 08:54 CDT 2021, Roja Rani Yarubandi wrote:
>
> > Add QSPI DT node for SC7280 SoC.
> >
> > Signed-off-by: Roja Rani Yarubandi <rojay@xxxxxxxxxxxxxx>
> > ---
> > Changes in V3:
> >  - Broken the huge V2 patch into 3 smaller patches.
> >    1. QSPI DT nodes
> >    2. QUP wrapper_0 DT nodes
> >    3. QUP wrapper_1 DT nodes
> >
> > Changes in V2:
> >  - As per Doug's comments removed pinmux/pinconf subnodes.
> >  - As per Doug's comments split of SPI, UART nodes has been done.
> >  - Moved QSPI node before aps_smmu as per the order.
> >
> >  arch/arm64/boot/dts/qcom/sc7280-idp.dts | 29 ++++++++++++
> >  arch/arm64/boot/dts/qcom/sc7280.dtsi    | 61 
> > +++++++++++++++++++++++++
> >  2 files changed, 90 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts 
> > b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > index 3900cfc09562..d0edffc15736 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
> > @@ -268,6 +268,22 @@ pmr735b_die_temp {
> >  		};
> >  };
> >
> > +&qspi {
> > +	status = "okay";
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
> > +
> > +	flash@0 {
> > +		compatible = "jedec,spi-nor";
> > +		reg = <0>;
> > +
> > +		/* TODO: Increase frequency after testing */
> > +		spi-max-frequency = <25000000>;
> > +		spi-tx-bus-width = <2>;
> > +		spi-rx-bus-width = <2>;
> > +	};
> > +};
> > +
> >  &qupv3_id_0 {
> >  	status = "okay";
> >  };
> > @@ -278,6 +294,19 @@ &uart5 {
> >
> >  /* PINCTRL - additions to nodes defined in sc7280.dtsi */
> >
> > +&qspi_cs0 {
> > +	bias-disable;
> > +};
> > +
> > +&qspi_clk {
> > +	bias-disable;
> > +};
> > +
> > +&qspi_data01 {
> > +	/* High-Z when no transfers; nice to park the lines */
> > +	bias-pull-up;
> > +};
> > +
> >  &qup_uart5_default {
> >  	tx {
> >  		pins = "gpio46";
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
> > b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 6c9d5eb93f93..3047ab802cd2 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -1061,6 +1061,42 @@ apss_merge_funnel_in: endpoint {
> >  			};
> >  		};
> >
> > +		qspi_opp_table: qspi-opp-table {
>
> This node doesn't represents anything on the mmio bus, so it shouldn't
> live in in /soc. Can't you move it into &qspi?
>
> Regards,
> Bjorn

Sure, will move it into qspi node.

Thanks,
Roja

> > +			compatible = "operating-points-v2";
> > +
> > +			opp-75000000 {
> > +				opp-hz = /bits/ 64 <75000000>;
> > +				required-opps = <&rpmhpd_opp_low_svs>;
> > +			};
> > +
> > +			opp-150000000 {
> > +				opp-hz = /bits/ 64 <150000000>;
> > +				required-opps = <&rpmhpd_opp_svs>;
> > +			};
> > +
> > +			opp-300000000 {
> > +				opp-hz = /bits/ 64 <300000000>;
> > +				required-opps = <&rpmhpd_opp_nom>;
> > +			};
> > +		};
> > +
> > +		qspi: spi@88dc000 {
> > +			compatible = "qcom,qspi-v1";
> > +			reg = <0 0x088dc000 0 0x1000>;
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> > +				 <&gcc GCC_QSPI_CORE_CLK>;
> > +			clock-names = "iface", "core";
> > +			interconnects = <&gem_noc MASTER_APPSS_PROC 0
> > +					&cnoc2 SLAVE_QSPI_0 0>;
> > +			interconnect-names = "qspi-config";
> > +			power-domains = <&rpmhpd SC7280_CX>;
> > +			operating-points-v2 = <&qspi_opp_table>;
> > +			status = "disabled";
> > +		};