On Wed 02 Jun 16:27 CDT 2021, Stephen Boyd wrote: > Quoting Jonathan Marek (2021-05-18 17:18:02) > > Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 > > bindings. Update the documentation with the new compatible. > > > > Signed-off-by: Jonathan Marek <jonathan@xxxxxxxx> > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > > --- > > .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- > > include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + > > > 2 files changed, 5 insertions(+), 2 deletions(-) > > create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h > > Why the symlink? Can we have the dt authors use the existing header file > instead? > > > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > index 0cdf53f41f84..8f414642445e 100644 > > --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml > > @@ -4,24 +4,26 @@ > > $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# > > $schema: http://devicetree.org/meta-schemas/core.yaml# > > > > -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 > > +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 > > Maybe just "Binding for SM8x50 SoCs" > That seems like a certain way to ensure that SM8450 etc will be different enough to not match this binding :) Regards, Bjorn
