On 18-05-21, 09:06, Jonathan Marek wrote:
> On 5/18/21 7:32 AM, Vinod Koul wrote:
> > > +static unsigned long
> > > +clk_zonda_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> > > +{
> > > + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> > > + u32 l, frac;
> > > +
> > > + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> > > + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
> > > +
> > > + return alpha_pll_calc_rate(parent_rate, l, frac, ALPHA_BITWIDTH);
> > > +}
> >
> > sounds like you could use clk_trion_pll_recalc_rate() instead
> >
>
> I had this thought as well, but alpha_width in clk_trion_pll_recalc()_rate
> is 16, here ALPHA_BITWIDTH is 32, so I just copied this from downstream.
>
> I think changing pll_alpha_width() to return the right value for zonda will
> work and allow sharing the function, if you think that's a good idea?
Yes I thinking pll_alpha_width() should do the trick here
Thanks
--
~Vinod
