Hi All,
On Wed, 2021-03-10 at 16:39 -0800, Guru Das Srinagesh wrote:
> Qualcomm's MFD chips have a top level interrupt status register and
> sub-irqs (peripherals). When a bit in the main status register goes
> high, it means that the peripheral corresponding to that bit has an
> unserviced interrupt. If the bit is not set, this means that the
> corresponding peripheral does not.
>
> Commit a2d21848d9211d ("regmap: regmap-irq: Add main status register
> support") introduced the sub-irq logic that is currently applied only
> when reading status registers, but not for any other functions like
> acking
> or masking. Extend the use of sub-irq to all other functions, with
> two
> caveats regarding the specification of offsets:
>
> - Each member of the sub_reg_offsets array should be of length 1
> - The specified offsets should be the unequal strides for each sub-
> irq
> device.
>
> In QCOM's case, all the *_base registers are to be configured to the
> base addresses of the first sub-irq group, with offsets of each
> subsequent group calculated as a difference from these addresses.
>
> Continuing from the example mentioned in the cover letter:
>
> /*
> * Address of MISC_INT_MASK = 0x1011
> * Address of TEMP_ALARM_INT_MASK = 0x2011
> * Address of GPIO01_INT_MASK = 0x3011
> *
> * Calculate offsets as:
> * offset_0 = 0x1011 - 0x1011 = 0 (to access MISC's
> * registers)
> * offset_1 = 0x2011 - 0x1011 = 0x1000
> * offset_2 = 0x3011 - 0x1011 = 0x2000
> */
>
> static unsigned int sub_unit0_offsets[] = {0};
> static unsigned int sub_unit1_offsets[] = {0x1000};
> static unsigned int sub_unit2_offsets[] = {0x2000};
>
> static struct regmap_irq_sub_irq_map chip_sub_irq_offsets[] = {
> REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
> REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
> REGMAP_IRQ_MAIN_REG_OFFSET(sub_unit0_offsets),
> };
>
> static struct regmap_irq_chip chip_irq_chip = {
> --------8<--------
> .not_fixed_stride = true,
> .mask_base = MISC_INT_MASK,
> .type_base = MISC_INT_TYPE,
> .ack_base = MISC_INT_ACK,
> .sub_reg_offsets = chip_sub_irq_offsets,
> --------8<--------
> };
>
> Signed-off-by: Guru Das Srinagesh <gurus@xxxxxxxxxxxxxx>
> ---
> drivers/base/regmap/regmap-irq.c | 81 ++++++++++++++++++++++++++--
> ------------
> include/linux/regmap.h | 7 ++++
> 2 files changed, 60 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/base/regmap/regmap-irq.c
> b/drivers/base/regmap/regmap-irq.c
> index 19db764..e1d8fc9e 100644
> --- a/drivers/base/regmap/regmap-irq.c
> +++ b/drivers/base/regmap/regmap-irq.c
> @@ -45,6 +45,27 @@ struct regmap_irq_chip_data {
> bool clear_status:1;
> };
>
Sorry that I am late with the "review" but I only now noticed this
change when I was following the references from PM8008 PMIC patch mail.
>
> +static int sub_irq_reg(struct regmap_irq_chip_data *data,
> + unsigned int base_reg, int i)
Do I read this correctly - this function should map the main status bit
(given in i) to the (sub)IRQ register, right? How does this work for
cases where one bit corresponds to more than one sub-register? Or do I
misunderstand the purpose of this function? (This is the case with both
the BD70528 and BD71828).
> +{
> + const struct regmap_irq_chip *chip = data->chip;
> + struct regmap *map = data->map;
> + struct regmap_irq_sub_irq_map *subreg;
> + unsigned int offset;
> + int reg = 0;
> +
> + if (!chip->sub_reg_offsets || !chip->not_fixed_stride) {
> + /* Assume linear mapping */
> + reg = base_reg + (i * map->reg_stride * data-
> >irq_reg_stride);
> + } else {
> + subreg = &chip->sub_reg_offsets[i];
> + offset = subreg->offset[0];
> + reg = base_reg + offset;
> + }
> +
> + return reg;
> +}
> +
> static inline const
> struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data
> *data,
> int irq)
> @@ -87,8 +108,7 @@ static void regmap_irq_sync_unlock(struct irq_data
> *data)
>
> if (d->clear_status) {
> for (i = 0; i < d->chip->num_regs; i++) {
> - reg = d->chip->status_base +
> - (i * map->reg_stride * d-
> >irq_reg_stride);
> + reg = sub_irq_reg(d, d->chip->status_base, i);
How does this work with the case where we have many subregs pointed by
single main-status register bit? If I read this correctly, then the
chip->num_regs can be greater than amount of meaningful main-status
bits and thus greater than amount of map entries.
I don't have BD71828 or BD70528 at home so I haven't tested this. So
hopefully I misunderstand something - but if I don't, then this change
will break the existing main-IRQ functionality. I will visit the office
later this week and I'll see if I have a chance to test this - but I
hope you can check your change still supports the case where one main
status IRQ bit signals more than one sub-register with active IRQs.
Best Regards
Matti Vaittinen
--
Matti Vaittinen, Linux device drivers
ROHM Semiconductors, Finland SWDC
K
iviharjunlenkki 1E
90220 OULU
FINLAND
~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~
Simon says - in Latin please.
"non cogito me" dixit Rene Descarte, deinde evanescavit
(Thanks for the translation Simon)
