On Thu, 8 Apr 2021 at 23:38, Rob Herring <robh@xxxxxxxxxx> wrote: > > On Thu, Apr 08, 2021 at 04:47:35AM +0300, Dmitry Baryshkov wrote: > > Separate qcom,gcc-sdm845 clock bindings from the clock-less > > qcom,gcc.yaml, so that we can add required clocks and clock-names > > properties. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > > --- > > .../bindings/clock/qcom,gcc-sdm845.yaml | 82 +++++++++++++++++++ > > .../devicetree/bindings/clock/qcom,gcc.yaml | 2 - > > 2 files changed, 82 insertions(+), 2 deletions(-) > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml > > > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml > > new file mode 100644 > > index 000000000000..4099b09ee9dd > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml > > @@ -0,0 +1,82 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Qualcomm Global Clock & Reset Controller Binding > > + > > +maintainers: > > + - Stephen Boyd <sboyd@xxxxxxxxxx> > > + - Taniya Das <tdas@xxxxxxxxxxxxxx> > > + > > +description: | > > + Qualcomm global clock control module which supports the clocks, resets and > > + power domains on SDM845 > > + > > + See also: > > + - dt-bindings/clock/qcom,gcc-sdm845.h > > + > > +properties: > > + compatible: > > + const: qcom,gcc-sdm845 > > + > > + clocks: > > + items: > > + - description: Board XO source > > + - description: Board active XO source > > + - description: Sleep clock source > > + - description: PCIE 0 Pipe clock source > > + - description: PCIE 1 Pipe clock source > > + > > + clock-names: > > + items: > > + - const: bi_tcxo > > + - const: bi_tcxo_ao > > + - const: sleep_clk > > + - const: pcie_0_pipe_clk > > + - const: pcie_1_pipe_clk > > + > > + '#clock-cells': > > + const: 1 > > + > > + '#reset-cells': > > + const: 1 > > + > > + '#power-domain-cells': > > + const: 1 > > + > > + reg: > > + maxItems: 1 > > + > > + protected-clocks: > > + description: > > + Protected clock specifier list as per common clock binding. > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + - '#reset-cells' > > + - '#power-domain-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + # Example for GCC for MSM8960: > > I've lost my QCom decoder ring. Is 8960 and 845 the same thing? No. Mea culpa. > > > + - | > > + #include <dt-bindings/clock/qcom,rpmh.h> > > + clock-controller@100000 { > > + compatible = "qcom,gcc-sdm845"; > > + reg = <0x100000 0x1f0000>; > > + clocks = <&rpmhcc RPMH_CXO_CLK>, > > + <&rpmhcc RPMH_CXO_CLK_A>, > > + <&sleep_clk>, > > + <&pcie0_lane>, > > + <&pcie1_lane>; > > + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", "pcie_1_pipe_clk"; > > + #clock-cells = <1>; > > + #reset-cells = <1>; > > + #power-domain-cells = <1>; > > + }; > > +... > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml > > index ee0467fb5e31..490edad25830 100644 > > --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml > > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml > > @@ -32,7 +32,6 @@ description: | > > - dt-bindings/clock/qcom,gcc-mdm9615.h > > - dt-bindings/reset/qcom,gcc-mdm9615.h > > - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660) > > - - dt-bindings/clock/qcom,gcc-sdm845.h > > > > properties: > > compatible: > > @@ -52,7 +51,6 @@ properties: > > - qcom,gcc-mdm9615 > > - qcom,gcc-sdm630 > > - qcom,gcc-sdm660 > > - - qcom,gcc-sdm845 > > > > '#clock-cells': > > const: 1 > > -- > > 2.30.2 > > -- With best wishes Dmitry
