Hi Jarvis,
On Wed, 7 Apr 2021 at 04:51, Jarvis Jiang <jarvis.w.jiang@xxxxxxxxx> wrote:
>
> Add support for T99W175 modems, this modem series is based on SDX55
> qcom chip. The modem is mainly based on MBIM protocol for both the
> data and control path.
>
> This patch was tested with Ubuntu 20.04 X86_64 PC as host
>
> Signed-off-by: Jarvis Jiang <jarvis.w.jiang@xxxxxxxxx>
> ---
> drivers/bus/mhi/pci_generic.c | 58 +++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c
> index 5cf44bcfe040..3e396c65a758 100644
> --- a/drivers/bus/mhi/pci_generic.c
> +++ b/drivers/bus/mhi/pci_generic.c
> @@ -260,6 +260,52 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {
> .dma_data_width = 32
> };
>
> +static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
> + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1),
> + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(16, "QMI1", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(17, "QMI1", 32, 0),
Are these QMI channels need to be exposed, vendors usually expose
either QMI+QMAP or MBIM (for data and control), here you expose
IP_HW0_MBIM as 'data' channel, so I would expect that MBIM is all you
need for the 'control' channel.
> + MHI_CHANNEL_CONFIG_UL(18, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(19, "IP_CTRL", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(20, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(21, "IPCR", 32, 0),
> + MHI_CHANNEL_CONFIG_UL(32, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_DL(33, "AT", 32, 0),
> + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2),
> + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3),
> +};
> +
> +static struct mhi_event_config mhi_foxconn_sdx55_events[] = {
> + MHI_EVENT_CONFIG_CTRL(0, 128),
> + MHI_EVENT_CONFIG_DATA(1, 128),
> + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
> + MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101)
> +};
> +
> +static struct mhi_controller_config modem_foxconn_sdx55_config = {
> + .max_channels = 128,
> + .timeout_ms = 20000,
> + .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels),
> + .ch_cfg = mhi_foxconn_sdx55_channels,
> + .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events),
> + .event_cfg = mhi_foxconn_sdx55_events,
> +};
> +
> +static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
> + .name = "foxconn-sdx55",
> + .fw = "qcom/sdx55m/sbl1.mbn",
> + .edl = "qcom/sdx55m/edl.mbn",
> + .config = &modem_foxconn_sdx55_config,
> + .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> + .dma_data_width = 32
> +};
> +
> static const struct pci_device_id mhi_pci_id_table[] = {
> { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306),
> .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info },
> @@ -269,6 +315,18 @@ static const struct pci_device_id mhi_pci_id_table[] = {
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
> .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b2), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b3), /* T99W175 (sdx55) */
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + /* DW5930e (sdx55), With eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> + /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */
> + { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1),
> + .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
> { }
> };
> MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
> --
> 2.25.1
>
