Baruch Siach wrote: > From: Balaji Prakash J <bjagadee@xxxxxxxxxxxxxx> > > DWC_USB3_GFLADJ and DWC_USB3_GUCTL registers contain options > to control the behavior of controller with respect to SOF and ITP. > The reset values of these registers are aligned for 19.2 MHz > reference clock source. This change will add option to override > these settings for reference clock other than 19.2 MHz > > Tested on IPQ6018 SoC based CP01 board with 24MHz reference clock. > > Signed-off-by: Balaji Prakash J <bjagadee@xxxxxxxxxxxxxx> > [ baruch: mention tested hardware ] > Signed-off-by: Baruch Siach <baruch@xxxxxxxxxx> > --- > .../devicetree/bindings/usb/dwc3.txt | 5 ++ > drivers/usb/dwc3/core.c | 52 +++++++++++++++++++ > drivers/usb/dwc3/core.h | 12 +++++ > 3 files changed, 69 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt > index 1aae2b6160c1..4ffa87b697dc 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > @@ -89,6 +89,11 @@ Optional properties: > - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ > register for post-silicon frame length adjustment when the > fladj_30mhz_sdbnd signal is invalid or incorrect. > + - snps,quirk-ref-clock-adjustment: Value for GFLADJ_REFCLK_* fields of GFLADJ > + register for reference clock other than 19.2 MHz is used. > + - snps,quirk-ref-clock-period: Value for REFCLKPER filed of GUCTL. This field > + indicates in terms of nano seconds the period of ref_clk. To calculate the > + ideal value, REFCLKPER = (1/ref_clk in Hz)*10^9. Why is this a quirk? It's not a quirk. The user can inform the ref_clk period to the controller here. The default value from GUCTL.REFCLKPER is a value from coreConsultant setting. The designer knows what period it should be and should properly set it if the default is not correctly set. BR, Thinh
