On Thu, Mar 25, 2021 at 10:50:57AM +0530, skakit@xxxxxxxxxxxxxx wrote: > Hi Matthias, > > On 2021-03-22 23:04, Matthias Kaehlcke wrote: > > Hi Satya, > > > > On Mon, Mar 22, 2021 at 06:50:47PM +0530, skakit@xxxxxxxxxxxxxx wrote: > > > Hi Matthias, > > > > > > On 2021-03-13 02:10, Matthias Kaehlcke wrote: > > > > Hi Satya, > > > > > > > > On Thu, Mar 11, 2021 at 04:10:29PM +0530, satya priya wrote: > > > > > Add PM7325/PM8350C/PMK8350/PMR735A peripherals such as PON, > > > > > GPIOs, RTC and other PMIC infra modules for SC7280. > > > > > > > > > > Signed-off-by: satya priya <skakit@xxxxxxxxxxxxxx> > > > > > --- > > > > > This patch depends on base DT and board files for SC7280 to merge > > > > > first > > > > > https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 > > > > > > > > > > arch/arm64/boot/dts/qcom/pm7325.dtsi | 60 ++++++++++++++++++++ > > > > > arch/arm64/boot/dts/qcom/pm8350c.dtsi | 60 ++++++++++++++++++++ > > > > > arch/arm64/boot/dts/qcom/pmk8350.dtsi | 104 > > > > > ++++++++++++++++++++++++++++++++++ > > > > > arch/arm64/boot/dts/qcom/pmr735a.dtsi | 60 ++++++++++++++++++++ > > > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++ > > > > > 5 files changed, 292 insertions(+) > > > > > create mode 100644 arch/arm64/boot/dts/qcom/pm7325.dtsi > > > > > create mode 100644 arch/arm64/boot/dts/qcom/pm8350c.dtsi > > > > > create mode 100644 arch/arm64/boot/dts/qcom/pmk8350.dtsi > > > > > create mode 100644 arch/arm64/boot/dts/qcom/pmr735a.dtsi > > > > > > > > > > diff --git a/arch/arm64/boot/dts/qcom/pm7325.dtsi > > > > > b/arch/arm64/boot/dts/qcom/pm7325.dtsi > > > > > new file mode 100644 > > > > > index 0000000..393b256 > > > > > --- /dev/null > > > > > +++ b/arch/arm64/boot/dts/qcom/pm7325.dtsi > > > > > @@ -0,0 +1,60 @@ > > > > > > > > ... > > > > > > > > > + polling-delay-passive = <100>; > > > > > + polling-delay = <0>; > > > > > > > > Are you sure that no polling delay is needed? How does the thermal > > > > framework > > > > detect that the temperatures is >= the passive trip point and that it > > > > should > > > > start polling at 'polling-delay-passive' rate? > > > > > > > > > > As the temp-alarm has interrupt support, whenever preconfigured > > > threshold > > > violates it notifies thermal framework, so I think the polling delay > > > is not > > > needed here. > > > > From the documentation I found it's not clear to me how exactly these > > interrupts work. Is a single interrupt triggered when the threshold is > > violated or are there periodic (?) interrupts as long as the temperature > > is above the stage 0 threshold? > > > > Why is 'polling-delay-passive' passive needed if there are interrupts? > > Maybe > > to detect that the zone should transition from passive to no cooling > > when the > > temperature drops below the stage 0 threshold? > > The PMIC TEMP_ALARM peripheral maintains an internal over-temperature stage: > 0, 1, 2, or 3. Stage 0 is normal operation below the lowest (stage 1) > threshold [usually 95 C]. When in stage 1, the temperature is between the > stage 1 and 2 thresholds [stage 2 threshold is usually 115 C]. Upon hitting > the stage 3 threshold [usually 145 C], the PMIC hardware will automatically > shut down the system. > > The TEMP_ALARM IRQ fires on stage 0 -> 1 and 1 -> 0 transitions. We > therefore set polling-delay = <0> since there is no need for software to > monitor the temperature periodically when operating in stage 0. Upon > crossing the stage 1 threshold, SW receives the IRQ and the thermal > framework hits its first trip changing the thermal zone to passive mode. > This then engages the 100 ms polling enabled via polling-delay-passive = > <100>. If the temperate keeps climbing and passes the stage 2 threshold, > the thermal framework hits the second trip (which is critical) and it > initiates an orderly shutdown. If the temperature drops below the stage 1 > threshold, then the thermal framework exits passive mode and stops polling. > This approach reduces/eliminates the software overhead when not at an > elevated temperature. Thanks for the clarification. With the interrupt only firing on stage 0 -> 1 and stage 1 -> 0 it makes sense. I was expecting interrupts on the other transitions too.
