Re: [PATCH v14 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings

[Stephen Boyd <swboyd@xxxxxxxxxxxx>]

Quoting Krishna Manikandan (2021-03-25 05:01:00)
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> new file mode 100644
> index 0000000..4a26bef
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DSI 10nm PHY
> +
> +maintainers:
> +  - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx>
> +
> +allOf:
> +  - $ref: dsi-phy-common.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: qcom,dsi-phy-10nm
> +      - const: qcom,dsi-phy-10nm-8998
> +
> +  reg:
> +    items:
> +      - description: dsi phy register set
> +      - description: dsi phy lane register set
> +      - description: dsi pll register set
> +
> +  reg-names:
> +    items:
> +      - const: dsi_phy
> +      - const: dsi_phy_lane
> +      - const: dsi_pll
> +
> +  vdds-supply:
> +    description: |
> +      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
> +      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - vdds-supply
> +
> +unevaluatedProperties: false

additionalProperties: false instead? This comment applies to the other
bindings in this patch.

> +
> +examples:
> +  - |
> +     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> +     #include <dt-bindings/clock/qcom,rpmh.h>
> +
> +     dsi-phy@ae94400 {
> +         compatible = "qcom,dsi-phy-10nm";
> +         reg = <0x0ae94400 0x200>,
> +               <0x0ae94600 0x280>,
> +               <0x0ae94a00 0x1e0>;
> +         reg-names = "dsi_phy",
> +                     "dsi_phy_lane",
> +                     "dsi_pll";
> +
> +         #clock-cells = <1>;
> +         #phy-cells = <0>;
> +
> +         vdds-supply = <&vdda_mipi_dsi0_pll>;
> +         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                  <&rpmhcc RPMH_CXO_CLK>;
> +         clock-names = "iface", "ref";
> +     };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> new file mode 100644
> index 0000000..72a00cc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DSI 14nm PHY
> +
> +maintainers:
> +  - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx>
> +
> +allOf:
> +  - $ref: dsi-phy-common.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: qcom,dsi-phy-14nm
> +      - const: qcom,dsi-phy-14nm-660
> +
> +  reg:
> +    items:
> +      - description: dsi phy register set
> +      - description: dsi phy lane register set
> +      - description: dsi pll register set
> +
> +  reg-names:
> +    items:
> +      - const: dsi_phy
> +      - const: dsi_phy_lane
> +      - const: dsi_pll
> +
> +  vcca-supply:
> +    description: Phandle to vcca regulator device node.
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - vcca-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> +     #include <dt-bindings/clock/qcom,rpmh.h>
> +
> +     dsi-phy@ae94400 {
> +         compatible = "qcom,dsi-phy-14nm";
> +         reg = <0x0ae94400 0x200>,
> +               <0x0ae94600 0x280>,
> +               <0x0ae94a00 0x1e0>;
> +         reg-names = "dsi_phy",
> +                     "dsi_phy_lane",
> +                     "dsi_pll";
> +
> +         #clock-cells = <1>;
> +         #phy-cells = <0>;
> +
> +         vcca-supply = <&vcca_reg>;
> +         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                  <&rpmhcc RPMH_CXO_CLK>;
> +         clock-names = "iface", "ref";
> +     };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
> new file mode 100644
> index 0000000..743806d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DSI 20nm PHY
> +
> +maintainers:
> +  - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx>
> +
> +allOf:
> +  - $ref: dsi-phy-common.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: qcom,dsi-phy-20nm
> +
> +  reg:
> +    items:
> +      - description: dsi pll register set
> +      - description: dsi phy register set
> +      - description: dsi phy regulator register set
> +
> +  reg-names:
> +    items:
> +      - const: dsi_pll
> +      - const: dsi_phy
> +      - const: dsi_phy_regulator
> +
> +  vcca-supply:
> +    description: Phandle to vcca regulator device node.
> +
> +  vddio-supply:
> +    description: Phandle to vdd-io regulator device node.
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - vddio-supply
> +  - vcca-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> +     #include <dt-bindings/clock/qcom,rpmh.h>
> +
> +     dsi-phy@fd922a00 {
> +         compatible = "qcom,dsi-phy-20nm";
> +         reg = <0xfd922a00 0xd4>,
> +               <0xfd922b00 0x2b0>,
> +               <0xfd922d80 0x7b>;
> +         reg-names = "dsi_pll",
> +                     "dsi_phy",
> +                     "dsi_phy_regulator";
> +
> +         #clock-cells = <1>;
> +         #phy-cells = <0>;
> +
> +         vcca-supply = <&vcca_reg>;
> +         vddio-supply = <&vddio_reg>;
> +
> +         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                  <&rpmhcc RPMH_CXO_CLK>;
> +         clock-names = "iface", "ref";
> +     };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
> new file mode 100644
> index 0000000..78f6b16
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Display DSI 28nm PHY
> +
> +maintainers:
> +  - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx>
> +
> +allOf:
> +  - $ref: dsi-phy-common.yaml#
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - const: qcom,dsi-phy-28nm-hpm
> +      - const: qcom,dsi-phy-28nm-lp
> +      - const: qcom,dsi-phy-28nm-8960
> +
> +  reg:
> +    items:
> +      - description: dsi pll register set
> +      - description: dsi phy register set
> +      - description: dsi phy regulator register set
> +
> +  reg-names:
> +    items:
> +      - const: dsi_pll
> +      - const: dsi_phy
> +      - const: dsi_phy_regulator
> +
> +  vddio-supply:
> +    description: Phandle to vdd-io regulator device node.
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - vddio-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> +     #include <dt-bindings/clock/qcom,rpmh.h>
> +
> +     dsi-phy@fd922a00 {
> +         compatible = "qcom,dsi-phy-28nm";
> +         reg = <0xfd922a00 0xd4>,
> +               <0xfd922b00 0x2b0>,
> +               <0xfd922d80 0x7b>;
> +         reg-names = "dsi_pll",
> +                     "dsi_phy",
> +                     "dsi_phy_regulator";
> +
> +         #clock-cells = <1>;
> +         #phy-cells = <0>;
> +
> +         vddio-supply = <&vddio_reg>;
> +
> +         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> +                  <&rpmhcc RPMH_CXO_CLK>;
> +         clock-names = "iface", "ref";
> +     };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
> new file mode 100644
> index 0000000..c81399f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
> @@ -0,0 +1,41 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI PHY common dt properties
> +
> +maintainers:
> +  - Krishna Manikandan <mkrishn@xxxxxxxxxxxxxx>
> +
> +description: |
> +  This defines the DSI PHY dt properties which are common for all
> +  dsi phy versions.
> +
> +properties:
> +  "#clock-cells":
> +    const: 1
> +
> +  "#phy-cells":
> +    const: 0
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Display AHB clock
> +      - description: Board XO source
> +
> +  clock-names:
> +    items:
> +      - const: iface
> +      - const: ref
> +
> +required:
> +  - clocks
> +  - clock-names

Why isn't #phy-cells and #clock-cells always required? I would guess
power-domains may also always be required.

> +
> +additionalProperties: true
> +...