Hello:
This patch was applied to qcom/linux.git (refs/heads/for-next):
On Thu, 18 Feb 2021 14:55:09 -0800 you wrote:
> At boot time the following happens:
> 1. Device core gets ready to probe our SPI driver.
> 2. Device core applies SPI controller's "default" pinctrl.
> 3. Device core calls the SPI driver's probe() function which will
> eventually setup the chip select GPIO as "unasserted".
>
> Thinking about the above, we can find:
> a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would
> have had them configured as "GENI" pins and not as "GPIO" pins.
> b) It turns out that our BIOS also happens to init these pins as
> "output" (even though it doesn't need to since they're not muxed as
> GPIO) but leaves them at the default state of "low".
> c) As soon as we apply the "default" chip select it'll switch the
> function to GPIO and stop driving the chip select high (which is
> how "GENI" was driving it) and start driving it low.
> d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the
> new method of gpio CS control"), when the SPI core inits things it
> inits the GPIO to be "deasserted". Prior to that commit the GPIO
> was left untouched until first use.
> e) When the first transaction happens we'll assert the chip select and
> then deassert it after done.
>
> [...]
Here is the summary with links:
- arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor
https://git.kernel.org/qcom/c/deb625f19bc8
You are awesome, thank you!
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