On 2021-02-26 01:11, Stephen Boyd wrote:
Quoting Sai Prakash Ranjan (2021-02-25 01:30:24)
Add a DT node for the AOSS QMP on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 65c1e0f2fb56..cbd567ccc04e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -368,6 +369,19 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ aoss_qmp: qmp@c300000 {
power-domain-controller@c300000? power-controller@c300000?
Its an AOSS message RAM and all other SM* SoCs have as qmp@
and the dt binding as well, I see only SM8150 with power-controller,
that should probably be fixed?
+ compatible = "qcom,sc7280-aoss-qmp";
+ reg = <0 0x0c300000 0 0x100000>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP
+
IPCC_MPROC_SIGNAL_GLINK_QMP
+
IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+ };
+
spmi_bus: qcom,spmi@c440000 {
Ick, should be spmi@
Not introduced by this patch but I'll pass on the comment.
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
Thanks,
Sai
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