Quoting Kuogee Hsieh (2021-02-18 12:55:04) > Allow supported link rate to be limited to the value specified at > dtsi. If it is not specified, then link rate is derived from dpcd > directly. Below are examples, > link-rate = <162000> for max link rate limited at 1.62G > link-rate = <270000> for max link rate limited at 2.7G > link-rate = <540000> for max link rate limited at 5.4G > link-rate = <810000> for max link rate limited at 8.1G > > Changes in V2: > -- allow supported max link rate specified from dtsi Please don't roll this into the patch that removes the limit. The previous version of this patch was fine. The part that lowers the limit back down should be another patch. We rejected link-rate in DT before and we should reject it upstream again. As far as I can tell, the maximum link rate should be determined based on the panel or the type-c port on the board. The dp controller can always achieve HBR3, so limiting it at the dp controller is incorrect. The driver should query the endpoints to figure out if they want to limit the link rate. Is that done automatically sometimes by intercepting the DPCD?
