Quoting Manivannan Sadhasivam (2021-01-17 20:11:55) > Add support for PLL found in Qualcomm SDX55 platforms which is used to > provide clock to the Cortex A7 CPU via a mux. This PLL can provide high > frequency clock to the CPU above 1GHz as compared to the other sources > like GPLL0. > > In this driver, the power domain is attached to the cpudev. This is > required for CPUFreq functionality and there seems to be no better place > to do other than this driver (no dedicated CPUFreq driver). > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> > --- Applied to clk-next
