On 2021-02-07 14:38, Baruch Siach wrote:
Hi Kathiravan T,
Thanks for your review.
On Fri, Feb 05 2021, Kathiravan T wrote:
On 2021-01-27 19:50, Baruch Siach wrote:
From: Kathiravan T <kathirav@xxxxxxxxxxxxxx>
Signed-off-by: Kathiravan T <kathirav@xxxxxxxxxxxxxx>
[baruch: adjust regs address/size; drop binding updates;
drop unsupported quirk properties]
Signed-off-by: Baruch Siach <baruch@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 8 ++++
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 48
++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index 99cefe88f6f2..5aec18308712 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -78,3 +78,11 @@ nand@0 {
nand-bus-width = <8>;
};
};
+
+&qusb_phy_1 {
+ status = "ok";
+};
+
+&usb2 {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 9fa5b028e4f3..d4a3d4e4a7e9 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -524,6 +524,54 @@ qrtr_requests {
};
};
+ qusb_phy_1: qusb@59000 {
+ compatible = "qcom,ipq6018-qusb2-phy";
+ reg = <0x0 0x059000 0x0 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
+ <&xo>;
+ clock-names = "cfg_ahb", "ref";
As per the bindings, ref clock should be 19.2MHz where the XO in
IPQ60xx is
24MHz. Did the USB enumerated successfully and able to perform read /
write
operations?
I managed to enumerate an Ethernet USB dongle with only this series
applied. But then I tested again with USB storage device. That only
worked with downstream clock adjust/period patch:
https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/commit/?h=fig&id=707d8fa2b481888f4792edc6561e81999301cbcf
That patch applies cleanly on top of v5.11-rc4.
Is anyone at Codeaurora pushing the dwc3 clock patch upstream? Should I
do that?
Sure, please go ahead.
Thanks,
baruch
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