Quoting Douglas Anderson (2021-01-14 15:40:27) > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 192ed31eabf4..712a693425fc 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -1097,16 +1128,11 @@ static int msm_gpio_irq_reqres(struct irq_data *d) > } > > /* > - * Clear the interrupt that may be pending before we enable > - * the line. > - * This is especially a problem with the GPIOs routed to the > - * PDC. These GPIOs are direct-connect interrupts to the GIC. > - * Disabling the interrupt line at the PDC does not prevent > - * the interrupt from being latched at the GIC. The state at > - * GIC needs to be cleared before enabling. > + * The disable / clear-enable workaround we do in msm_pinmux_set_mux() > + * only works if disable is not lazy since we only clear any bogus > + # interrupt in hardware. Explicitly mark the interrupt as UNLAZY. Ah! What is # doing there? > */ > - if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) > - irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, 0); > + irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); >
