Hi, On Wed, Dec 16, 2020 at 8:29 PM Stephen Boyd <swboyd@xxxxxxxxxxxx> wrote: > > > The SPI core in general assumes that setting chip select is a simple > > operation that doesn't fail. Yet another reason to just reconfigure > > the chip select line as GPIOs. > > BTW, we could peek at the irq bit for the CS change and ignore the irq > handler entirely. That would be one way to make sure the cs change went > through, and would avoid an irq delay/scheduling problem for this simple > operation. Maybe using the irq path is worse in general here? Yes, when I was in my SPI optimization phase I actually coded this up and thought about it. It can be made to work and is probably marginally faster at the expense of more cpu cycles to poll the interrupt line. I also don't think it fixes this issue nor does it simplify things... :( 1. If there are already commands pending we still have to do something about them. Said another way: there's not a separate channel just for setting the chip select, so if the single command channel is gummed up then using polling mode to handle the chip select won't really un-gum it up. 2. In order to use polling mode to set the chip select we have to do _something_ to temporarily disable our interrupt handler. If we don't do that then the interrupt handler will fire for the "DONE" when we send the chip select command. If we wanted to truly make this driver super robust against ridiculous interrupt latencies then, presumably, we could handle the SPI timeout ourselves but before timing out we could check to see if the interrupts were pending. Then we could disable our interrupts, synchronize our interrupt handler, handle the interrupt directly, and then re-enable interrupts. If we did this then transfers could continue to eek their way through even if interrupts were completely blocked. IMO, it's not worth it. I'm satisfied with not crashing and not getting the state machine too out-of-whack. -Doug
