On Sat 26 Sep 08:03 CDT 2020, kholk11@xxxxxxxxx wrote:
> From: AngeloGioacchino Del Regno <kholk11@xxxxxxxxx>
>
> It is required for optimal performance and to avoid MDP stalls to
> retain mem/periph on GDSC enablement: to achieve this, let's add
> the required CXC to the MDSS GDSC.
>
Can you please explain how you came to this conclusion, I don't see the
reference to the MDP_CLK_SRC in the downstream kernel.
Thanks,
Bjorn
> Signed-off-by: AngeloGioacchino Del Regno <kholk11@xxxxxxxxx>
> ---
> drivers/clk/qcom/mmcc-sdm660.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
> index 234aca7c873b..7b1384cf8506 100644
> --- a/drivers/clk/qcom/mmcc-sdm660.c
> +++ b/drivers/clk/qcom/mmcc-sdm660.c
> @@ -2572,6 +2572,8 @@ static struct gdsc mdss_gdsc = {
> .pd = {
> .name = "mdss",
> },
> + .cxcs = (unsigned int []){ 0x2040 },
> + .cxc_count = 1,
> .pwrsts = PWRSTS_OFF_ON,
> };
>
> --
> 2.28.0
>
